NewMaterials Engineer Intern (Spring & Summer 2027) ZiplineMaterials Engineer Intern (Spring & Summer 2027)San Francisco, CAExamples of previous intern projects include designing, building, testing, and running: flexible blind-mate ducting connection between an aircraft and a ground-based cooling station, allowing for aircraft battery temperature regulation during charging and pre-flight preparation. Mechanical Engineers at Zipline go deep in their area of ownership, become experts in the problem domain, define requirements for their systems, rapidly develop creative and simple solutions, and prove with testing that their system meets the rigors and edge-cases of real-world deployment.
Staff Electrical Engineer – Test Systems E-SpaceStaff Electrical Engineer – Test SystemsSaratoga, CAYou will work collaboratively with engineers of various disciplines to develop the automated test framework for satellite avionics and systems including test methods, custom PCBAs, harnesses, and other hardware, and ultimately support the rigorous flight-like testing of satellite hardware. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet.
NewPower Electronics Engineer, Energy Storage Redwood MaterialsPower Electronics Engineer, Energy StorageSan Francisco, CA$125,000–$242,500 / yearThis role involves solving practical circuit- and system-level challenges in converter topology, power-stage component selection (e.g., MOSFETs and magnetics), PCB/PCBA design, thermal analysis, integration, and validation. In this role, you will design advanced power converters that interface with battery packs, battery modules, photovoltaic (PV) systems, and the grid for large-scale energy storage applications, including AI datacenters.
Sr Staff Reliability Engineer Aviso, LLCSr Staff Reliability EngineerFremont, CAFull timeApply Advanced Methodologies: Utilize reliability engineering tools such as Weibull analysis, Reliability Modeling, Fault Tree Analysis, Accelerated Life Testing (ALT), HALT/HASS, and structured root cause analysis to drive data-based design decisions. Define Requirements: Establish reliability requirements, reliability growth plans, and demonstration strategies for NPI (New Product Introduction) programs and sustaining design changes; devise test protocols and author comprehensive test reports.
Materials Engineer NeuralinkMaterials EngineerSouth San Francisco, CA$113,000–$209,000 / yearOwn the in-house mechanical testing pipeline end-to-end: design fixtures, prepare specimens, run tests (servo-hydraulic, drop tower, DIC), and correlate results to simulation using quantitative metrics (CORA, force-displacement overlay, DIC contour comparison). This person will build explicit dynamics FEA models, design and run physical tests, calibrate material models against experimental data, and validate predictions.
NewSr. Site Development Engineer Mariana MineralsSr. Site Development EngineerSan Francisco, CaliforniaYou will lead civil, grading, drainage, utilities, and site infrastructure design, manage external engineering partners, and support the development of internal tools and workflows for efficient capital project execution. You will work cross-functionally across engineering, construction, and project delivery teams to ensure sites are designed for constructability, scalability, and long-term operational performance.
Analog Design Engineer Omnivision TechnologiesAnalog Design EngineerSanta Clara, CA$156,853–$160,000 / yearJob Title: Analog Design Engineer Job Duties:Conduct design and development of image sensor technologies, work on transistor level design of analog and mixed-signal circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp generator, ASRAM and XDEC by using Cadence Virtuoso. Design the internal Discrete-time Circuits, Peripheral circuits and Timing control for a CMOS image sensor, including bias circuits, driver/level shifter, switched capacitor, logic gates and slew rate control.
RF Test Engineer CYNET SYSTEMSRF Test EngineerMountain View, CA$50–$55 / hourTemporaryContractorPart timePerform Radiated/Conducted TRP/TIS/aGPS Testing, in signaling or non-signaling mode, using test chambers, including but not limited to, R&S Anechoic chamber; BlueTest Chamber; GTS chamber, etc. Perform RF System Testing on devices for design verification and system validation, including controlled (conducted and radiated) test environment tests for RF performance, interference, noise floor (RSSI), coexistence (multiple-radios), throughput, etc.
Senior Asic Design Engineer Cornelis NetworksSenior Asic Design EngineerSan Jose, CARemoteCornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols-including TCP/IP, RDMA/RoCE, and IPSec-and their application in high-speed data processing and networking environments.
NewStaff Electrical Engineer OusterStaff Electrical EngineerSan Francisco, CA$154,000–$230,000 / yearExpert-level with Altium (or similar), with specific, deep personal experience in HDI anylayer, rigid-flex, and high-density multi-layer PCBs taken to series production. Track record of architecting and delivering embedded SoC (DSP + ARM, or FPGA + ARM) systems, with deep knowledge of Ethernet, CAN, I2C, SPI, and USB.
Design Engineer MetriportDesign EngineerSan Francisco, CaliforniaWe've found product-market fit with multi-million ARR, 100+ customers (including Amazon One Medical, Strive Health, Circle Medical, and Brightside Health), backing from top VCs, and years of runway. As a Design Engineer at Metriport, you'll spend your time understanding customer workflows, designing the best solution to those problems, and implementing your own designs.
Sr. Analog Design Engineer OmnivisionSr. Analog Design EngineerSanta Clara, CaliforniaPerform the block level and transistor level layout design and optimization of sensor array readout circuits using CAD tools like Cadence Virtuoso and Calibre. Collaborate with verification, process, test, and application engineers to debug, characterize and optimize performance of fabricated image sensors and successfully bring new products from initial concept through release.
Principal Physical Design Engineer, Methodology Astera LabsPrincipal Physical Design Engineer, MethodologySan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Sr. Staff Analog Design Engineer OmnivisionSr. Staff Analog Design EngineerSanta Clara, California$170,000–$240,000 / yearPerform the block level and transistor level layout design and optimization of sensor array readout circuits using CAD tools like Cadence Virtuoso and Calibre. Collaborate with verification, process, test, and application engineers to debug, characterize and optimize performance of fabricated image sensors and successfully bring new products from initial concept through release.
Analog Mixed-Signal Design Engineer Omnivision TechnologiesAnalog Mixed-Signal Design EngineerSanta Clara, CA$156,853–$160,000 / yearExpertise in programming using Python, perl, scilab and Cshell; Experience with EDA tools such as Cadence Virtuoso, Cadence Simvision, Cadence Layout in circuit design; Experience in RTL level functional block behavioral verification; Experience in using Hspice, Spectre to build-up analog circuit test bench to perform transistor level simulation on analog/mixed-signal circuits. Job Title: Analog Mixed-Signal Design EngineerJob Duties: Design, develop, and characterize embedded analog circuits, such as high speed I/O, SerDes, FIFO, CDR, PLL, etc.
NewStaff Analog Design Engineer, Tx/Rx Datapath D-MatrixStaff Analog Design Engineer, Tx/Rx DatapathSanta Clara, CAThe work spans porting proven datapath blocks to new process nodes and ground-up design of new blocks for our next-generation link, working closely with layout, package/signal-integrity, backend, and firmware engineers to bring your designs to working silicon. Build the verification environment for your blocks - testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, and post-layout back-annotated simulation - and provide behavioral and Verilog-A models for full-chip verification, supporting backend engineers through integration.
Senior Electrical Engineer Kennedy/Jenks ConsultantsSenior Electrical EngineerSan Francisco, CA$115,000–$165,000 / yearThis role offers a unique opportunity to join our growing team and help shape the design of water and wastewater infrastructure projects, including treatment facilities, pump stations, buildings, and related systems. Technical knowledge: Technical expertise in MCCs, switchboards, panelboards, load calculations, diesel generators, medium- and low-voltage power systems, transformers, MV/LV switchgear, and SKM software.
Project Engineer - Structural Hellmuth Obata & Kassabaum, IncProject Engineer - StructuralSan Francisco, CAProject Engineers will be responsible for the successful delivery of small to medium size building projects, or working as part of a large team responsible for an area on major projects, including developing concepts and producing the design. Experience with potential project types in commercial, corporate, institutional and civic, justice, aviation, and healthcare sectors is a plusMechanical: Experience with complex analysis tools and energy modeling for mechanical design.
Signal Integrity Engineer - Serdes, Satellites (Starlink) SpaceXSignal Integrity Engineer - Serdes, Satellites (Starlink)Palo Alto, CA$115,000–$155,000 / yearWork alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers (among others) to architect new products which will employ novel channels, interfaces, and power delivery strategies. As a Signal Integrity Engineer on Starlink’s Payload Engineering team, you’ll have SI ownership throughout the entire life-cycle of the portfolio of hardware that enables this connectivity, and sits at the intersection of electrical, mechanical, thermal analysis, software, and antenna/RF engineering.
NewPrincipal PLL Design Engineer Celero CommunicationsPrincipal PLL Design EngineerSan Jose, California$150,000–$250,000 / yearWe are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. • Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre.