NewDFT Engineer (Design for Test) Plugins IncDFT Engineer (Design for Test)Santa Clara, CA$70,000–$90,000 / yearContractorFull timeIn this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions that ensure high manufacturing quality, test coverage, and efficient production testing for complex semiconductor devices. We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team.
Physical Design Engineer Einfochips (An Arrow electronics company)Physical Design EngineerSan Jose, CA$110,000–$130,000 / yearContractorFull timeContribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Staff ASIC Design Engineer Celero CommunicationsStaff ASIC Design EngineerSan Jose, CaliforniaCelero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.) .
NewSenior ASIC Design Engineer - Hardware NVIDIA GruppeSenior ASIC Design Engineer - HardwareSanta Clara, CAThis position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor‑planning, ECO, bring‑up & lab debug.
ASIC Design Engineer Hewlett Packard Enterprise CompanyASIC Design EngineerSunnyvale, CAFull timeAccountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
Sr. Engineer, ASIC Design Ayar LabsSr. Engineer, ASIC DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
ASIC/SoC Design Engineer, RTL design for SoC IPs Advanced Micro Devices IncASIC/SoC Design Engineer, RTL design for SoC IPsSan Jose, CAKnowledge of ARM architecture and AMBA protocol specifications Familiarity with PCIe or CXL transaction layer protocols Experience with low-power design techniques (clock gating, power gating, voltage scaling) Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting Exposure to formal verification tools for equivalence checking and property verification Familiarity with AI-assisted design tools and modern EDA technologies Experience mentoring junior engineers and leading design teams Strong technical writing skills for design specifications and documentation Excellent communication and collaboration skills in cross-functional environments. RTL Design & Microarchitecture: • Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
Senior ASIC Design Engineer Zp Group LlcSenior ASIC Design EngineerSaratoga, CA$250,000–$290,000 / yearKeywords: ASIC, ASIC Architect, Networking ASIC, AI Networking, Design, Microarchitecture, Performance Modeling, PCIe, SerDes, Ethernet, TCP/IP, RoCE, High-Speed Datapath, Silicon Validation, System-on-Chip, SoC Architecture, Hardware Design, IP Integration, Physical Design, Firmware Interface, Chip Architect, DPU, CPU, SOC. Qualifications for Senior ASIC Design Engineer: 10+ years of experience as an Chip Architect, preferably in networking or high-performance computing (Routers, Switches, GPU, CPU, Data Center, etc).
NewSenior ASIC Design Engineer - SoC Bring-up Ayar LabsSenior ASIC Design Engineer - SoC Bring-upSan Jose, CAThe ideal candidate will have a BS or MS in Electrical or Computer Engineering with 1+ years of experience in ASIC design and proficiency in Verilog and ASIC verification tools.#J-18808-Ljbffr. This role requires a hands-on self-starter to work in a dynamic startup environment, collaborating closely with a small IC design team.
NewSenior ASIC Design Engineer - Co-Packaged Optics Ayar LabsSenior ASIC Design Engineer - Co-Packaged OpticsSan Jose, CA$180,000–$223,000 / yearThis role offers an opportunity to work in a fast-paced startup environment with competitive remuneration ranging from $180,000 to $223,000.#J-18808-Ljbffr. The ideal candidate will have a BS or MS in Electrical Engineering and over 5 years of experience in ASIC design and verification.
ASIC Design Engineer lll Hewlett Packard EnterpriseASIC Design Engineer lllSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. The successful candidate will be responsible for the microarchitecture, RTL implementation, integration, and bring-up of high-performance networking IPs and subsystems used in next-generation switch, router, SmartNIC, DPU, and AI networking products.
ASIC Design Engineer lll Hewlett Packard Enterprise CoASIC Design Engineer lllSunnyvale, CA$120,000–$243,000 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
NewSenior ASIC Design Engineer - Agentic AI NVIDIA GruppeSenior ASIC Design Engineer - Agentic AISanta Clara, CA$168,000–$264,500 / yearWhat you'll be doing: As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications. As part of the AI for Chip Design team, you will develop agentic AI solutions to craft the micro‑architecture, implement the RTL, and deliver a fully verified, synthesis/timing clean design.
NewASIC Design Engineer NVIDIA GruppeASIC Design EngineerSanta Clara, CA$116,000–$189,750 / yearWhat we need to see BS/MS Degree or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science.2+ years of relevant RTL design work experience. What you'll be doing Drafting microarchitecture documents and implementing high-performance, area, and power-efficient RTL to meet strictly defined development targets and specifications.
NewASIC Design Engineer RTL & Microarchitecture (Equity) NVIDIA GruppeASIC Design Engineer RTL & Microarchitecture (Equity)Santa Clara, CA$116,000–$189,750 / yearIdeal candidates hold a BS/MS in electrical engineering, have at least 2 years of RTL design experience, and showcase strong skills in Verilog and coding languages. The position offers a competitive salary range of $116,000 – $189,750 for Level2 and $136,000 – $218,500 for Level3.#J-18808-Ljbffr.
SR ASIC SoC Design Engineer Advanced Micro Devices IncSR ASIC SoC Design EngineerSanta Clara, CAWe are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production. THE TEAM: Our group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generation AI networking workloads.
NewASIC Design Engineer, ML Processor & Digital IP Advanced Micro DevicesASIC Design Engineer, ML Processor & Digital IPSan Jose, CAOverviewAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers to PCs, gaming and embedded systems. The RoleAs a frontend ASIC Design Engineer, ML Processor & Digital IP, you will work on defining and implementing features in key IPs.
ASIC Design Engineer - Neural Engine DMA Apple IncASIC Design Engineer - Neural Engine DMASunnyvale, CAWorking closely with design verification and formal verification teams to ensure functional correctness: reviewing test plans, debugging failures, and ensuring the designs intended behavior is fully exercised. In this front-end design role, your work will include: Writing well-parameterized RTL structured for correct synthesis, clean timing, and low power, along with assertions and cover points that encode design intent and ensure verification completeness.
ASIC Design Engineer Hewlett Packard EnterpriseASIC Design EngineerSunnyvale, CaliforniaAccountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more} What We Can Offer You: Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
Principal ASIC Design Engineer Hewlett Packard Enterprise CoPrincipal ASIC Design EngineerSunnyvale, CA$174,000–$352,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
ASIC Design Engineer Hewlett Packard Enterprise CoASIC Design EngineerSunnyvale, CA$120,000–$243,000 / yearAdditional Skills: Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
Principal ASIC Design Engineer Hewlett Packard EnterprisePrincipal ASIC Design EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
SR ASIC Design Engineer - NoC & AXI Interconnect Advanced Micro Devices IncSR ASIC Design Engineer - NoC & AXI InterconnectSanta Clara, CAAs a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O Advanced Micro Devices IncSR ASIC Design Engineer - Ethernet Switch & High-Speed I/OSanta Clara, CAAs a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
Sr. Staff Engineer, ASIC Design Ayar LabsSr. Staff Engineer, ASIC DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
Sr. Engineer, ASIC Design Ayar Labs IncSr. Engineer, ASIC DesignSan Jose, CA$160,000–$192,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
NewML Processor ASIC Design Engineer - Frontend Digital IP Advanced Micro DevicesML Processor ASIC Design Engineer - Frontend Digital IPSan Jose, CAThe ideal candidate will hold a degree in Computer Engineering or Electrical Engineering and possess strong analytical skills to tackle complex challenges. Advanced Micro Devices is seeking a Frontend ASIC Design Engineer, specializing in ML Processor & Digital IP, to define and implement features in key IPs.
Sr. ASIC Design Engineer (Video Silicon IP) - Multimedia Lab Beijing ByteDance Technology Co LtdSr. ASIC Design Engineer (Video Silicon IP) - Multimedia LabSan Jose, CAThe successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), in-loop filters, and etc.
ASIC Design Engineer (Video Silicon IP) - Multimedia Lab Beijing ByteDance Technology Co LtdASIC Design Engineer (Video Silicon IP) - Multimedia LabSan Jose, CAThe successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. Team Introduction The Video Silicon IP team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users.
ASIC Design Engineer Qualcomm IncASIC Design EngineerSanta Clara, CA$126,700–$190,100 / yearQCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. Required Skill: 5+ years of industry experience in ASIC design, micro-architecture, and design integration, Strong background in SoC micro-architecture, including specification, definition, and implementation of functional blocks.
Senior ASIC Design Engineer, Google Cloud Google LLCSenior ASIC Design Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Sr. ASIC Design Engineer MicronSr. ASIC Design EngineerSan Jose, CaliforniaAs a Senior ASIC Design Engineer and domain expert, you will perform logic design across the full ASIC lifecycle from specifications and microarchitecture to design, integration, synthesis, timing, linting, and CDC. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
NewSenior Cellular ASIC Design Engineer - Power & PPA Apple, Inc.Senior Cellular ASIC Design Engineer - Power & PPASunnyvale, CAA leading technology company is seeking a Cellular ASIC Design Engineer to develop and optimize the design and methodology for integrated circuits in advanced process technologies. The role requires a strong VLSI background, with responsibilities including timing closure, power optimization, and collaboration with cross-functional teams.
ASIC Design Engineer (eInfochips) Arrow Electronics IncASIC Design Engineer (eInfochips)Mountain View, CAAlong with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.
NewASIC Design Verification Engineer (Hardware Security) Qualcomm IncASIC Design Verification Engineer (Hardware Security)Santa Clara, CA$153,200–$229,800 / yearThe Hardware Security team works on cutting edge security solution products for premium Snapdragon chip sets and is seeking Hardware Design engineers with solid ASIC design experience in San Diego, CA. The work will expose the candidate to all aspects of hardware security product creation flow, including Architecture, Microarchitecture, Design, Validation, IP development, Synthesis, Timing closure, Layout, and thorough Silicon Testing.
NewSenior ASIC Design Engineer - Clocks IP NVIDIA GruppeSenior ASIC Design Engineer - Clocks IPSanta Clara, CAImprove Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking. Preferred Qualifications Experience with clocks controller, clocks logic designUnderstanding of system level artifacts like power, noise, etcExperience with scalable designs and architecture.
ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration Amazon.com IncASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning AccelerationCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
NewMTS Silicon ASIC Design Engineer Advanced Micro DevicesMTS Silicon ASIC Design EngineerSanta Clara, CAThis role involves defining architectures, verifying designs, and collaborating with engineers to solve complex issues in electronic design. Advanced Micro Devices is seeking an MTS Silicon Design Engineer to lead research and development for semiconductor components.
ASIC Design Engineer Apple IncASIC Design EngineerSanta Clara, CAKnowledge of high-performance memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram interface calibration/training mechanisms and algorithms is a plus. As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day.
NewSenior Wireless ASIC Design Engineer Apple, Inc.Senior Wireless ASIC Design EngineerSunnyvale, CA$181,100–$318,400 / yearCompetitive salary range from $181,100 to $318,400 based on qualifications and experience, with additional benefits including stock options, medical coverage, and educational reimbursement.#J-18808-Ljbffr. This role involves RTL design of wireless MACs, creating specifications, and ensuring high performance low power ASIC designs.
NewCellular ASIC Design Engineer Apple, Inc.Cellular ASIC Design EngineerSunnyvale, CA$181,100–$318,400 / yearYou'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. DescriptionAs a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power optimization, and design technology co-optimization.
ASIC Design Engineer - Pixel IP DMA Apple IncASIC Design Engineer - Pixel IP DMACupertino, CAWorking with design verification and formal verification teams to verify functionality and performanceBachelors Degree + 0 years of experienceExperience in multimedia IP/SoC front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal communication skills Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks. As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs Amazon.com IncASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna LabsCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
NewSenior ASIC Design Engineer for AI-Driven Chip Design NvidiaSenior ASIC Design Engineer for AI-Driven Chip DesignSanta Clara, CACandidates should possess a Master's or PhD in Electrical Engineering, with substantial experience in micro-architecture and RTL development.#J-18808-Ljbffr. NVIDIA Corporation is seeking an experienced ASIC Design Engineer to join the 'AI for chip design' team.
ASIC Design Engineer - Cache Controller Apple IncASIC Design Engineer - Cache ControllerSanta Clara, CAWork with physical design team on the timing closure of the cache subsystem.10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background including an understanding of different memory organizations and tradeoffs. Hands on Experience with multi-processor cache coherence protocols B.S. in a relevant fieldKnowledge of high-performance coherent memory systems or interconnect architectures Knowledge of high-performance DRAM controller M.S in a relevant field.
ASIC Design Engineer Marvell Technology IncASIC Design EngineerCAStrong background in high-performance DSP and high-speed datapath design, including pipelined arithmetic units, algorithm-driven hardware implementation, packet processing engines, memory subsystems, and large-scale control/state machines. • Drive post-silicon bring-up and debug, collaborating with lab and systems teams to validate functionality, characterize performance, and resolve complex issues across datapath, DSP, and protocol layers.
NewSr. ASIC Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpSr. ASIC Design Verification Engineer Silicon EngineeringPalo Alto, CA$175,000–$280,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
NewASIC RTL/SoC Design Engineer TetraMemASIC RTL/SoC Design EngineerSan Jose, CA$110,000–$300,000 / yearAbility to work with the backend teamFamiliarity with AMBA APB AXI ProtocolFamiliarity with RISC/Arm or other core architecturesAbility to create innovative architecture and solutions to customer requirementsAbility to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team. Experience in one or more of the following areas considered a strong plusFPGA/ASIC design of image processing systemsWorking knowledge of SoC architecture such as CPU, GPU or acceleratorsFamiliarity with: UVM, place‑and‑route, STA, EM/IR/PowerSalary Range: $110,000 - $300,000 / year#J-18808-Ljbffr.
Principal Engineer - Digital ASIC Design Microchip Technology IncPrincipal Engineer - Digital ASIC DesignSan Jose, CA$70,304–$163,000 / yearOur company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence.
NewSenior ASIC/SoC Design Engineer: RTL to Tape-out Advanced Micro DevicesSenior ASIC/SoC Design Engineer: RTL to Tape-outSan Jose, CAThe ideal candidate has extensive experience with RTL coding, ASIC design flow, and strong leadership skills to mentor junior engineers. You will oversee the complete RTL design lifecycle, ensuring high-quality delivery of production silicon.