DFT (Design for Test) Engineer Plugins IncDFT (Design for Test) EngineerSanta Clara, CA$50–$90 / hourContractorFull timeWe are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug.
NewPhysical Design Engineer II (IC) Arrow Electronics, Inc.Physical Design Engineer II (IC)San Jose, CA$87,400–$165,000 / yearContribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
NewFormal Verification Engineer ExperisFormal Verification EngineerSanta Clara, CA$70–$80 / hourGuided by the belief that it takes Human Ingenuity to unlock the true potential of technology, Experis helps people gain experience with leading organizations, build sought-after skills and take the next step toward a brighter future. Backed by ManpowerGroup's 75+ years of workforce expertise and global reach across more than 70 countries and territories, Experis brings the scale, insight and opportunity to help people and businesses thrive.
NewSenior Software Development Engineer, AWS Machine Learning Accelerators Annapurna Labs (U.S.) Inc.Senior Software Development Engineer, AWS Machine Learning AcceleratorsCupertino, CAAs a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. We pioneered cloud computing and never stopped innovating — that’s why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.
NewPrincipal Hardware Engineer, DC/DC Power MicrosoftPrincipal Hardware Engineer, DC/DC PowerMountain View, CA$142,800–$274,800 / yearDoctorate in Electrical Engineering, Computer Engineering, or related field AND 3+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, or related field AND 6+ years technical engineering experience. To achieve this goal, the CHSE (Cloud Hardware Systems Engineering) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.
ASIC Design Engineer – DSP / Analog / SerDes Celero CommunicationsASIC Design Engineer – DSP / Analog / SerDesSan Jose, California$150,000–$250,000 / yearStrong knowledge of one or more of the following areas: - Digital Signal Processing (DSP) - High-speed SerDes - Analog/Mixed-Signal ICs - Digital communications - Optical communications • Experience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.• What You Will Bring • Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field.• 5+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.•
Senior Asic Design Engineer Cornelis NetworksSenior Asic Design EngineerSan Jose, CARemoteCornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols-including TCP/IP, RDMA/RoCE, and IPSec-and their application in high-speed data processing and networking environments.
Pcie Asic Design Engineer Cornelis NetworksPcie Asic Design EngineerSan Jose, CARemoteIn addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions.
ML ASIC Design Engineer Waymo LLCML ASIC Design EngineerMountain View, CA$175,000–$215,000 / yearSince its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World''s Most Experienced Driver-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states.
Senior ASIC Design Engineer Zp Group LlcSenior ASIC Design EngineerSaratoga, CA$250,000–$290,000 / yearKeywords: ASIC, ASIC Architect, Networking ASIC, AI Networking, Design, Microarchitecture, Performance Modeling, PCIe, SerDes, Ethernet, TCP/IP, RoCE, High-Speed Datapath, Silicon Validation, System-on-Chip, SoC Architecture, Hardware Design, IP Integration, Physical Design, Firmware Interface, Chip Architect, DPU, CPU, SOC. Qualifications for Senior ASIC Design Engineer: 10+ years of experience as an Chip Architect, preferably in networking or high-performance computing (Routers, Switches, GPU, CPU, Data Center, etc).
ASIC Design Engineer 2 Hewlett Packard EnterpriseASIC Design Engineer 2Sunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
NewASIC Design Engineer 2 Hewlett Packard Enterprise CoASIC Design Engineer 2Sunnyvale, CA$105,500–$213,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
NewAsic Design Engineer 2 Hewlett Packard EnterpriseAsic Design Engineer 2Sunnyvale, CA$105,500–$213,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
ASIC Design Engineer Epia NeuroASIC Design EngineerAlameda, CaliforniaBachelor's degree in Electrical Engineering/Computer Science, plus relevant industry experience in ASIC design — or a Master's/PhD with hands-on ASIC design experience through university lab or project work. The company’s initial focus is stroke-related motor impairment, with expansion in cognitive decline and other neurological disorders, focusing on long-term solutions for the growing aging population.
ASIC Design Engineer - Neural Engine DMA Apple IncASIC Design Engineer - Neural Engine DMASunnyvale, CAWorking closely with design verification and formal verification teams to ensure functional correctness: reviewing test plans, debugging failures, and ensuring the designs intended behavior is fully exercised. In this front-end design role, your work will include: Writing well-parameterized RTL structured for correct synthesis, clean timing, and low power, along with assertions and cover points that encode design intent and ensure verification completeness.
Mid Level ASIC Design Engineer Recogni IncMid Level ASIC Design EngineerSunnyvale, CAAbout the role: As a member of Tensordyne's ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC.This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power. Your responsibilities will be wide-ranging and run the gamut of microarchitecture design and documentation, Verilog RTL implementation, selecting and integration 3rd-party IP blocks, working closely with design verification engineers, running frontend synthesis and working with a backend team on place-and-route guidance and timing closure.
ASIC Design and Integration Engineer - Silicon Security Apple IncASIC Design and Integration Engineer - Silicon SecurityCupertino, CAYour responsibilities will include: Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time. In this role, you will design the state-of-the-art hardware defenses that prevent complex side channel attacks and ensure the integrity of our customers most sensitive data across Apples product line.
Principal Asic Design Engineer Hewlett Packard EnterprisePrincipal Asic Design EngineerSunnyvale, CA$174,000–$352,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
Principal ASIC Design Engineer Hewlett Packard EnterprisePrincipal ASIC Design EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
Principal ASIC Design Engineer Hewlett Packard Enterprise CoPrincipal ASIC Design EngineerSunnyvale, CA$174,000–$352,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.