Burlington, VT30+ days ago
Play a leading role in developing full-custom SRAM memory layout and sign-off verification flows • Collaborate with circuit designers to translate schematics into efficient, high-performance layouts and drive end-to-end ownership from floor planning to tape-out. • Ensure physical verification closure by resolving DRC, LVS, ERC, antenna violations, and custom memory checks • Lead layout reviews, mentor junior engineers, and promote best practices, optimization techniques, and design rule compliance while fostering knowledge-sharing and process improvements.