Santa Clara, California22 days ago
li style="margin-left:0.25in;font-size:12pt;font-family:'arial' , 'helvetica' , sans-serif">Develop solution sets tied to key EDA and CAE workloads (e.g., RTL/logic simulation, physical verification, place-and-route, static timing analysis, DRC/LVS, SPICE, emulation, AI/ML-driven chip design), with joint value propositions and go-to-market plans to accelerate growth. Conduct competitive, market, and partner capability assessments to shape actionable vertical expansion plans, and build the frameworks (market analysis, vendor evaluation, business case, partnership execution) that support them.