Hardware & Silicon Validation Principal Engineer MarvellHardware & Silicon Validation Principal EngineerSanta Clara, CAThe Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators. The group validates complex, high performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing.
Principal Engineer, AI Tooling And Workflows NvidiaPrincipal Engineer, AI Tooling And WorkflowsSanta Clara, CAIn this role, you will define and build agentic AI systems, developer productivity platforms, and intelligent workflow automation that accelerate software delivery across NVIDIA's engineering organization. Partner with engineering leaders, teams across products, infrastructure, security, and research to identify high-leverage opportunities and deliver solutions with broad impact.
Principal Engineer Synthesis Team Lattice Semiconductor CorpPrincipal Engineer Synthesis TeamSan Jose, CaliforniaLattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. You will drive industry-leading outcomes across maximum frequency (Fmax), area efficiency, runtime performance, and memory utilization—balancing tradeoffs to meet the demands of diverse customer use cases.
Senior Principal Embedded Firmware Software Engineer - Networking Pam4 Dsp/Data Center/Odsp/Aec/Microled/Ai Connectivity MarvellSenior Principal Embedded Firmware Software Engineer - Networking Pam4 Dsp/Data Center/Odsp/Aec/Microled/Ai ConnectivitySanta Clara, CAThe Optical Digital Signal Processing (ODSP) PHY SW Team develops software for Marvell's DSP products used in pluggable optical modules-chips that form the backbone of the internet, moving data within and between data centers worldwide. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Principal Test Engineer MarvellPrincipal Test EngineerSanta Clara, CALead Cutting-Edge ATE Test Solutions: As a Senior Level Test Engineer, you will spearhead the development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K and/or Teradyne tester platforms. Optimize and Innovate: Play a lead role in optimizing test flows, reducing test times, removing unnecessary steps, improving yields, and releasing production test programs in collaboration with product engineers.
Principal Test Development Engineer MarvellPrincipal Test Development EngineerSanta Clara, CALead Cutting-Edge ATE Test Solutions: As a Senior Level Test Engineer, you will spearhead the development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K and/or Teradyne tester platforms. Optimize and Innovate: Play a lead role in optimizing test flows, reducing test times, removing unnecessary steps, improving yields, and releasing production test programs in collaboration with product engineers.
Principal Physical Design Engineer Astera LabsPrincipal Physical Design EngineerSan Jose, CA$185,000–$230,000 / yearAs a Principal Engineer on the Physical Design team, you will own the backend implementation of complex, high-performance SoCs that sit at the heart of the world's largest AI clusters - driving floorplan, timing, power, and signoff decisions that directly determine product PPA and time-to-market. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Principal Digital RTL Engineer Astera LabsPrincipal Digital RTL EngineerSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. You'll own designs from specification through silicon bring-up, set the technical direction for complex AMS blocks, and mentor engineers across the team - turning ambitious architecture into production-proven products that ship at scale.
Principal Engineer, HBM Field Application SK hynixPrincipal Engineer, HBM Field ApplicationSan Jose, CA$190,000–$230,000 / yearOur cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies.
Principal Engineer, Product Compliance Bloom EnergyPrincipal Engineer, Product ComplianceSan Jose, CaliforniaOur cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm. For over two decades, we’ve been at the forefront of the global energy transition, pioneering solutions that empower critical industries to thrive in a rapidly digitizing, energy-intensive world.
Sr Principal Engineer, Enclosures Design Bloom EnergySr Principal Engineer, Enclosures DesignSan Jose, CaliforniaThey have experience in the automotive industry having delivered cars and trucks to the vehicle marketplace, or in NEMA 4X compliant enclosures, sealing strategies and manufacturing approaches that survive real world deployment for decades. Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm.
Principal Electrical Engineer, NPI Bloom EnergyPrincipal Electrical Engineer, NPIFremont, CaliforniaOur cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm. For over two decades, we’ve been at the forefront of the global energy transition, pioneering solutions that empower critical industries to thrive in a rapidly digitizing, energy-intensive world.
Principal Engineer, Laser Controls Ayar LabsPrincipal Engineer, Laser ControlsSan Jose, CaliforniaKey Responsibilities Define and own the end-to-end laser module control architecture, including: APC (Automatic Power Control) loops for stable optical output, ACC (Automatic Current Control) strategies for laser drive optimization, Automatic calibration frameworks (power, current, aging compensation, temperature drift), and TEC (Thermoelectric Cooler) control for wavelength and thermal stability. Backed by industry giants like NVIDIA, Mediatek, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.
Principal Engineer, System Validation Ayar LabsPrincipal Engineer, System ValidationSan Jose, CaliforniaThis role owns reliability qualification at the system and fleet level: building the test infrastructure and evidence base that proves our products are ready for large-scale deployment, and then partnering directly with customers and integration partners to carry that evidence through joint qualification programs and pilot deployments. Fault injection and lifecycle monitoring: Design and run fault-injection and failure-mode testing, including scenarios that exercise field-serviceable components under representative operating conditions, in partnership with customer and integration-partner operations teams.
Principal Engineer, Mapping and Localization PlusAIPrincipal Engineer, Mapping and LocalizationSanta Clara, CADesign and implement robust, real-time algorithms for sensor fusion, visual/LiDAR odometry, and global localization using techniques like Factor Graphs, EKF/UKF, and particle filters. You will tackle the hardest edge cases—from GPS-denied tunnels to dynamic construction zones—ensuring our vehicles operate safely in complex L4 ODDs (Operational Design Domains).
Principal Engineer, Verification MarvellPrincipal Engineer, VerificationSanta Clara, CAHighlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major telecom organization or automotive company, etc.
Senior Principal Engineer - Hardware Chip Lead, Connectivity BU MarvellSenior Principal Engineer - Hardware Chip Lead, Connectivity BUSanta Clara, CAOur products - including multi-terabit retimers, coherent DSP devices, and high-speed optical transceivers - are critical enablers for efficient, high-bandwidth data transmission across fiber optical networks and electrical interconnects at 100G+ per lane. We are a global, multi-site engineering organization spanning Santa Clara, Ottawa, Pavia, Irvine, Vietnam, and Argentina - and we are looking for a senior experienced technical leader to serve as Hardware Chip Lead on our next-generation ODSP programs.
Hardware & Silicon Validation Senior Principal Engineer MarvellHardware & Silicon Validation Senior Principal EngineerSanta Clara, CAThe group validates complex, high performance silicon and platforms across a wide range of critical technologies and interfaces, including Memory Subsystems (DDR, HBM, memory controllers), High Speed Interconnects (PCIe, Ethernet, CPRI, PAM4/NRZ), D2D interconnects, Storage, and IO (Flash and NVME, SSD controllers, USB) and System and Platform testing. The Custom Cloud Solutions (CCS) Hardware Validation Group is responsible for ensuring the quality, reliability, and performance of next generation data center ASIC and SoC products spanning a diverse portfolio that includes cloud infrastructure, AI accelerators, network processors, NICs, custom ASICs, SSD controllers, CXL devices, and domain specific accelerators.
Principal Hardware Engineer - IO & Memory Systems SambaNova Systems, Inc.Principal Hardware Engineer - IO & Memory SystemsSan Jose, CA$180,000–$255,000 / yearPowered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. You will operate across silicon, board, and software layers-leading cross-functional teams to root cause, driving issues to resolution, and building the infrastructure that makes future bring-up cycles faster and more reliable.
NewPrincipal Post-Silicon Validation Engineer SambaNova Systems, Inc.Principal Post-Silicon Validation EngineerSan Jose, CAPowered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. The Post-Silicon Validation team bring up and validate the high-speed IO and memory subsystems inside SambaNova's DataScale platform, including PCIe, Ethernet, HBM, CXL, and UCIe interfaces.