Software Engineering Intern, Power Modeling & AI Tools Tenstorrent UniversitySoftware Engineering Intern, Power Modeling & AI ToolsSanta Clara, CaliforniaYour work will include integrating and analyzing engineering data, developing internal tools and scripts, creating visualizations and AI-enabled interfaces, and supporting workload profiling, model validation, and analytics to improve power model accuracy and reliability. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
Principle Validation And Hardware Design Engineer MarvellPrinciple Validation And Hardware Design EngineerSanta Clara, CAMarvell, a high-speed analog/mixed-signal semiconductor company, is the market leader in high-speed and optical interconnects for communication infrastructure in long-haul, metro and datacenter. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Principal Serdes Bring-Up Validation Engineer Astera LabsPrincipal Serdes Bring-Up Validation EngineerSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization), with the ability to investigate jitter sources, CDR/PLL behavior, crosstalk, and power integrity issues.
Analog IC Layout Engineer NeuralinkAnalog IC Layout EngineerSouth San Francisco, CA$83,000–$139,000 / yearJob Description and Responsibilities: We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces.
Senior Staff Post-Silicon Validation Engineer MarvellSenior Staff Post-Silicon Validation EngineerSanta Clara, CAPurpose-built to scale data center compute fabrics inside accelerated servers, general-purpose servers, CXL systems and disaggregated infrastructure, the Alaska P PCIe retimer line features best-in-class SerDes performance, ultra-low power dissipation, low latency, and a rich feature set including advanced diagnostics and telemetry. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Staff Engineer, HIL Design, Hardware Integration & Test Cariad, Inc.Staff Engineer, HIL Design, Hardware Integration & TestMountain View, CA$161,710–$234,325 / yearThe Staff Engineer, HIL Design, Hardware Integration & Test owns the hardware-oriented architecture, build, bring-up, and sustained readiness of HIL benches, integration benches, harnesses, Interface Control Documents (ICDs), and AI-enabled lab automation used to validate CARIAD, Inc. hardware platforms. Hands-on integration and debug of display interfaces, analog audio, digital audio, RF/radio communication paths, CAN/CAN FD, LIN, Ethernet/1000BASE-T1, serial, USB, UART, SPI, I2C, GPIO, analog/digital I/O, power/wake lines, and diagnostics.
L3 IT Service Desk Engineer ZonesL3 IT Service Desk EngineerSan Jose, CAFull timeOperating in more than 120 countries, leveraging a robust portfolio, and utilizing the highest certification levels from key partners, including Microsoft, Apple, Cisco, Lenovo, Adobe, and more, Zones has mastered the science of building digital infrastructures that change the way business does business ensuring whatever they need, they can Consider IT Done. Position Overview: Term: 6-month contract to hire Location: on-site in San Jose California Pay: up to $39/hr Hours: M-F- 8-5pm What you will do as the L3 IT Service Desk Engineer: You will help provide technical information to education and service teams,and may assist with teaching and presenting technical hardware/software to many audiences.
Optical Test Engineer, Principal Astera LabsOptical Test Engineer, PrincipalSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. This senior role drives optical and electro-optical testing for next-generation high-bandwidth CPO modules and optical engines integrated with ASICs for AI, hyperscale data centers, and high-performance computing.
Opto-Mechanical Engineer AetherfluxOpto-Mechanical EngineerSan Carlos, CaliforniaMechanical Integration: Work closely with the mechanical engineering team to design and integrate opto-mechanical systems for satellite platforms, ensuring that optical components can withstand the rigors of space. Laser System Design & Integration: Design and model laser systems, including solid-state, fiber, or semiconductor lasers, and integrate them with mechanical structures for space deployment.
Controls Engineer Mind RoboticsControls EngineerPalo Alto, CaliforniaWe believe the hardest problems in AI are solved when researchers and engineers are hands-on with the physical world every day - and we're looking for people who are passionate about robotics, value ownership, and are excited to tackle difficult problems. We're looking for a Controls Engineer to own the algorithms and software that make our robots move well — from low-level actuator loop design to full-body motion control and the simulation infrastructure that keeps us iterating fast.
Staff Engineer - Vehicle And Propulsion Architecture Knightscope Inc.Staff Engineer - Vehicle And Propulsion ArchitectureSunnyvale, CA$180,000–$210,000 / yearIn this role, you will be the technical owner of the master CAD assembly and the powertrain system, balancing packaging, manufacturability, serviceability, cost, and performance as you integrate mechanical, electrical, and software subsystems into a cohesive vehicle. Knightscope (NASDAQ: KSCP) is a security technology company building the nation's first Autonomous Security Force - autonomous machines, AI-driven software, and elite security professionals operating as one integrated managed service.
Antenna Design Engineer Array LabsAntenna Design EngineerRedwood City, CaliforniaITAR Requirements: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. In forging an affordable, accessible, accurate representation of Earth, our work has the potential to transform the face of dozens of fields, including autonomy, telecommunications, disaster relief, gaming, climate science, defense and construction.
Senior Principal Digital Design Engineer Astera LabsSenior Principal Digital Design EngineerSan Jose, CA$205,000–$255,000 / yearThis is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Rack Level Integration Engineer MarvellRack Level Integration EngineerSanta Clara, CABachelor's degree in Mechanical Engineering, Electrical Engineering or related fields and 3-5 years of related professional experience or Master's degree and/or PhD in Mechanical Engineering, Electrical Engineering or related fields with 2-3 years of experience or equivalent professional experience in lieu of a formal degree. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Principal Digital Design Engineer Astera LabsPrincipal Digital Design EngineerSan Jose, CA$185,000–$230,000 / yearYou'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Design Verification Infrastructure Sr. Staff Engineer MarvellDesign Verification Infrastructure Sr. Staff EngineerSanta Clara, CABachelor's degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience or equivalent professional experience in lieu of a formal degree. A deterministic Python framework owns everything that decides pass/fail and everything that must be reproducible - build, run, verdict, coverage, and the quality gates - while an AI layer sits on top for the judgment-heavy work: deciding what to run, triaging failures, and proposing fixes that a human approves.
Principal Product Engineer - AI Cloud & Data Center MarvellPrincipal Product Engineer - AI Cloud & Data CenterSanta Clara, CAHighlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. Become empowered as a key decision-maker for Marvell's portfolio of Ethernet and Data center products from New Production Introduction (NPI) to Mass Production Release (MPR).
IP Release Principal Engineer MarvellIP Release Principal EngineerSanta Clara, CAOwn and execute the IP delivery checklist at each milestone (iRTL, Code Complete, RTLF), verifying completeness of all required collateral including: RTL source files, file manifests (.f/.vc), SDC, UPF, memory lists, CDC crossing lists, static waivers, CSR/register descriptions, synthesis scripts, and integration guidelines. Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree.
Tech Lead Physical Design Engineer, Power Integrity Astera LabsTech Lead Physical Design Engineer, Power IntegritySan Jose, CA$160,000–$200,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Test Development Engineer MarvellPrincipal Test Development EngineerSanta Clara, CALead Cutting-Edge ATE Test Solutions: As a Senior Level Test Engineer, you will spearhead the development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K and/or Teradyne tester platforms. Optimize and Innovate: Play a lead role in optimizing test flows, reducing test times, removing unnecessary steps, improving yields, and releasing production test programs in collaboration with product engineers.