Review specifications, extract features, define and execute verification plan Develop top/block level Mixed Signal and Digital testbench and generate tests in a UVM framework Build and reuse monitors, and checkers for RF/Mixed-Signal blocks Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage Write scripts for automation of flow Improve Mixed Signal verification methodology with novel ideas and leveraging AI Collaborate with the Analog Design TeamBS and a minimum of 10 years relevant industry experience Industry verification experience with RF/Mixed-Signal blocks and SOCs Expertise building Mixed-Signal testbenches, checkers and tests using System Verilog Experience in UVM methodology and HDL (System Verilog, Verilog) for verification Strong verification skills in problem solving, testing, and debugging Understanding of common analog/RF blocks Experience with UPF, Python or Matlab a plus Experience with Virtuoso Composer, ADE, and HED also a plusMasters or PhD degree in technical disciplines with at least 5+ years of hands-on experience in specifically Mixed-Signal verification Wireless experience is a plus Expertise creating and using real-numbered analog behavioral models in System Verilog a plus. All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering.