Senior Test Engineer - (107895) SanminaSenior Test Engineer - (107895)San Jose, CA$108,000–$155,000 / yearThe total rewards package also includes a variety of benefits, including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business and, depending on the role, may include eligibility for restricted stock unit awards andparticipation in a discretionary bonus program. Sanmina is recognized as a technology leader, providing end-to-end design, manufacturing and logistics solutions, maintaining a global footprint of design and manufacturing operations in 23 countries on six continents.
IT Engineer A-StaffingIT EngineerSan Jose, CaliforniaPerform troubleshooting for remote & on-site server, PC, network, telephony hardware, and software for customers. Provide supports of server, PC, network, telephony hardware, and software administration to customers.
Forward Deployed Engineer - AI Partnerships (Teradyne Robotics, San Jose, CA) Teradyne, Inc.Forward Deployed Engineer - AI Partnerships (Teradyne Robotics, San Jose, CA)San Jose, CA$125,700–$201,200 / yearYou will work directly with leading AI model builders, robotics startups, and strategic partners to help them build, validate, and deploy applications on Teradyne's robotics platforms, including Universal Robots (UR) and Mobile Industrial Robots (MiR). Your primary responsibility is to ensure partners can successfully leverage our robotics platform stack (control, motion, interfaces, Polyscope integration) to bring their products to life in real-world environments.
AI Systems Engineer Advanced Micro Devices, IncAI Systems EngineerSan Jose, CaliforniaIn this role, you will work at the intersection of hardware and software, designing high-performance ML operator kernels, optimizing dataflow pipelines, and enabling industry-leading AI inference performance across AMD NPU and GPU platforms. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
Software Engineering Technical Leader - Networking CiscoSoftware Engineering Technical Leader - NetworkingSan Jose, CaliforniaThe applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $186,900.00 - $307,800.00 Non-Metro New York state & Washington state: $166,300.00 - $274,100.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.
Electrical Engineer ArchKey Solutions LLCElectrical EngineerSan Jose, CA$111,000–$133,200 / yearFull timeThis role bridges engineering and construction by working closely with field electricians, project managers, designers, and VDC/BIM teams to deliver fully constructible designs across a wide range of projects, from small Design/Build efforts to some of the largest hyper-scale construction projects in the country. In addition to permit drawing development, the Electrical Engineer reviews outside engineering documents for accuracy and constructability, identifies value engineering opportunities, as well as perform engineering studies such as arc flash, short circuit, duct bank ampacity, power factor correction, and lighting.
NewTechnical Lead Package Platform Engineer Astera LabsTechnical Lead Package Platform EngineerSan Jose, CA$160,000–$200,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
RF Hardware Engineer - Multi-Radio Coexistence Artech LLCRF Hardware Engineer - Multi-Radio CoexistenceCupertino, CA$100–$100.45 / hourKnowledge of RF component characteristics and experience using lab equipment including spectrum analyzer, network analyzer, signal generator, oscilloscopes, call box. Design bench experiments, collect performance data & analyze wireless logs across various RF parameters to derive HW specification for various multi-radio coexistence use-cases.
NewPackaging Tech Lead Design Engineer Astera LabsPackaging Tech Lead Design EngineerSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
NewStaff AI Observability & Telemetry Engineer BitdeerStaff AI Observability & Telemetry EngineerSan Jose, CAYou will capture, store, and make sense of millions of hardware and software signals per second, enabling our SREs, automated remediation agents, and external customers to peer deep into the performance of their GPU workloads and the underlying network fabric. Architect and scale a high-cardinality telemetry infrastructure using highly available time-series databases (e.g., VictoriaMetrics, Thanos, or Mimir) capable of handling massive ingestion rates.
NewSenior mixed-signal electrical engineer (Board Level) ASMLSenior mixed-signal electrical engineer (Board Level)San Jose, CaliforniaLead the design, analysis, and implementation of high-performance analog and mixed-signal circuits on board level , including: High-speed (>50 MSPS), high-precision (16-bit) DAC/ADC signal chains. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members.
NewPrincipal Mechanical Engineer QuantumScape Corp.Principal Mechanical EngineerSan Jose, CA$136,700–$184,500 / yearSkills You'll Need: Bachelor's degree or higher in Mechanical Engineering, Mechatronics, Manufacturing Engineering, Aerospace Engineering, Materials Science, or a related technical discipline, with 10+ years of experience (BS), 8+ years (MS), or 5+ years (PhD) in mechanical design, automation, tooling, equipment development, manufacturing scale-up, or related engineering environments. About the team: The Hardware, Automation, and Metrology team develops first-of-its-kind automation, tooling, precision mechanical systems, and metrology-enabled equipment used to scale QuantumScape's solid-state lithium-metal battery manufacturing processes from proof-of-concept through production qualification.
Mandarin - Engineer Project Manager BYDMandarin - Engineer Project ManagerCupertino, CaliforniaWork closely with sales and procurement teams to define competitive pricing strategies based on material costs, production feasibility, and market trends. 5+ years of experience in mechanical engineering, product assembly, or manufacturing, with a focus on metal enclosures, casings, or structural components.
Optical Validation Engineer, Principal Astera LabsOptical Validation Engineer, PrincipalSan Jose, CA$160,000–$200,000 / yearWe are seeking an experienced Optical (EIC/PIC) Validation Engineer at the Principal level to lead the validation, characterization, and qualification of advanced photonic integrated circuits (PICs) closely integrated with electronic integrated circuits (EICs) multiple optical configurations. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Principal Optical Assembly Engineer Astera LabsPrincipal Optical Assembly EngineerSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. This is a high-impact individual contributor role with technical leadership responsibilities, focused on developing robust assembly processes, expanding lab capability, and improving the yield, quality, and reliability of optical assemblies for NPO and CPO products.
Fabric Modeling And Analysis Engineer For Scale Up Fabric Astera LabsFabric Modeling And Analysis Engineer For Scale Up FabricSan Jose, CA$185,000–$240,000 / yearServe as the internal authority on fabric modeling, partnering with ASIC architects and product teams to drive roadmap and feature decisions, support early customer engagement, and produce modeling reports, white papers, and presentations for engineering, product, and executive audiences. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Advanced Package Engineer, Principal Astera LabsAdvanced Package Engineer, PrincipalSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Digital RTL Engineer Astera LabsPrincipal Digital RTL EngineerSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. You'll own designs from specification through silicon bring-up, set the technical direction for complex AMS blocks, and mentor engineers across the team - turning ambitious architecture into production-proven products that ship at scale.
Principal Physical Design Engineer Astera LabsPrincipal Physical Design EngineerSan Jose, CA$185,000–$230,000 / yearAs a Principal Engineer on the Physical Design team, you will own the backend implementation of complex, high-performance SoCs that sit at the heart of the world's largest AI clusters - driving floorplan, timing, power, and signoff decisions that directly determine product PPA and time-to-market. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Principal IP Signoff & Methodology Engineer Astera LabsPrincipal IP Signoff & Methodology EngineerSan Jose, CA$175,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.