Sr. Staff Security Engineer - AI, Vmr, Offensive Security Geico InsuranceSr. Staff Security Engineer - AI, Vmr, Offensive SecurityPalo Alto, CA$120,000–$260,000 / yearThis role blends deep security engineering expertise with strong architectural leadership, hands-on experience, leveraging frontier AI models for security, drive customer success, and provide advisory to senior executive leaders. You are equally comfortable advising executive leadership as you are designing and building secure systems, bringing a rare blend of strategic influence and deep engineering execution to elevate the organization's security posture.
Senior Firmware Engineer TacitSenior Firmware EngineerSan Francisco, CaliforniaYou’ll work closely with electrical, mechanical, software, ML, and product teams to transition systems from prototype to robust, production-ready products while helping establish strong firmware engineering practices across the company. As a key member of our growing firmware team, you will own major portions of the embedded software stack from early architecture through production and play a critical role in bringing complex consumer electronics to life.
Senior Fpga Design Engineer (Mtd, San Jose, CA) Teradyne, Inc.Senior Fpga Design Engineer (Mtd, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Fpga Design Engineer (Mtd, San Jose, CA) Teradyne, Inc.Fpga Design Engineer (Mtd, San Jose, CA)San Jose, CA$135,400–$216,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior FPGA Design Engineer (MTD, San Jose, CA) TeradyneSenior FPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world’s most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
FPGA Design Engineer (MTD, San Jose, CA) TeradyneFPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$135,400–$216,600 / yearOur test instrumentation supports the world’s most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
NewSenior Failure Analysis Engineer (Semiconductor / Electronics) Eurofins USA Material SciencesSenior Failure Analysis Engineer (Semiconductor / Electronics)Sunnyvale, CAOur parent company, Eurofins Scientific, is a multi-billion-dollar global leader in engineering and scientific services operating over 950 labs in 60 countries with 65,000 employees with a portfolio of over 200,000 validated analytical methods. Using advanced techniques in analytical chemistry, microscopy, surface analysis, and engineering sciences, we help clients solve complex challenges across the product lifecycle.
System Engineer, DSP Arycs Technologies, Inc.System Engineer, DSPLos Gatos, CAWork as a key member of the DSP ASIC system engineering team to innovate, develop and validate system-level models of coherent DSP algorithms (both in floating-point and fixed-point arithmetic), and analog RF and optical devices housed in our optical transceivers. About the role As the System Engineer of Coherent Optical DSP and Transceivers, you will join a small team and play a pivotal role in the design, development, testing, and validation of optical transceivers for use in datacom and telecom networks.
SR. SatCom Engineer HFSS- Hybrid / Remote Associates SystemsSR. SatCom Engineer HFSS- Hybrid / RemoteSan Jose, CaliforniaRemoteEducation Bachelor’s or Master’s degree in Electrical Engineering, Aerospace Engineering, Telecommunications, or a related field. We are seeking a highly skilled SATCOM Engineer to support the design, operation, and optimization of next‑generation space and ground communication technologies.
Senior Asset Pipeline Engineer - Sensor Platform Applied IntuitionSenior Asset Pipeline Engineer - Sensor PlatformSunnyvale, CaliforniaAT APPLIED INTUITION, YOU WILL: Design the OpenUSD schema and composition strategy — references, variants, payloads, custom schemas — for a large, versioned 3D asset library that must scale across authoring tools and simulation engines. Solve material conversion for simulation: translate complex authored materials into USD-native representations (UsdShade, and MDL where needed) while preserving the physical fidelity sensor simulation requires — not just visual appearance.
Staff Software Engineer, Product Quality Recruiting From ScratchStaff Software Engineer, Product QualitySan Francisco, CaliforniaThe company is hiring a Staff Engineer to own quality across testing, CI, release infrastructure, and provider integrations—building systems that automatically catch regressions and upstream model-provider changes without slowing engineering velocity. Design and build comprehensive provider conformance testing covering streaming, tool calling, structured outputs, authentication, error mapping, and cost tracking.
Newwire harness engineer Technical Talent Groupwire harness engineerBerkeley, CAThis role requires close collaboration with Electrical, Mechanical, Manufacturing, and Supply Chain teams to deliver production-ready harness solutions capable of supporting large-scale deployment. As they transition a flagship product from development into high-volume manufacturing, they are seeking an experienced Wire Harness Design Engineer with deep expertise in both mechanical harness design and Zuken E3 to support the next phase of product development.
NewStaff Mechanical Engineer – HV & LV Harness Design Technical Talent GroupStaff Mechanical Engineer – HV & LV Harness DesignSan Francisco, CAThe ideal candidate brings deep experience designing complex harness systems for high-volume electromechanical products and can balance performance, reliability, manufacturability, cost, and serviceability throughout the product lifecycle. We are seeking a Staff Mechanical Engineer to lead the mechanical design and development of low-voltage and high-voltage wire harness systems for large-scale battery and energy storage platforms.
Navi — Founding Hardware Engineer DavidJoseph&CoNavi — Founding Hardware EngineerSan Francisco, CaliforniaThe person joins the technical side alongside the CTO and lead software engineer as one of the first ten employees, and must be deeply hands-on, able to reason through a six-month hardware roadmap with full architectural clarity, and comfortable making consequential decisions with limited precedent. Tech stack: PCB / schematic design, microcontrollers, embedded C/C++ or Python, RTOS or embedded Linux, wireless modules (cellular / Wi-Fi / Bluetooth), edge-to-cloud streaming, OTA update infrastructure, cloud telemetry dashboards.
Senior Mechanical Design Engineer QuantumScape Corp.Senior Mechanical Design EngineerSan Jose, CA$112,500–$163,000 / yearPartner closely with systems, controls, electrical, process, manufacturing, and EHS teams to deliver integrated equipment solutions across all phases of the design lifecycle, including specifications, design reviews, prototyping, assembly, testing, FAT/SAT, and continuous improvement. Own mechanical design scope end to end, from early concept definition through detailed design, build, qualification, and handoff to manufacturing, with accountability for technical decisions, risk mitigation, and design readiness.
Board Design Engineer Array LabsBoard Design EngineerRedwood City, California$150,000–$250,000 / yearTo conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Hands-on experience laying out high-performance platforms including compute (SoCs, FPGAs, MCUs), storage (DDR, SSDs), high-speed interfaces (PCIe, SPI, JESD204B), RF components (PAs, LNAs, switches).
Principal Product Application Engineer - Leo Astera LabsPrincipal Product Application Engineer - LeoSan Jose, CA$175,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Sr. Fpga Design & Verification Engineer Dolby Sound LaboratoriesSr. Fpga Design & Verification EngineerSan Francisco, CA$137,100–$188,300 / yearDolby's consumer entertainment and cinema businesses are bringing Dolby's breakthrough technologies, powering the world's top movies, TV shows, music, games, and live sports to more places around the world across a wider range of consumer experiences and devices. Using disciplined engineering practices such as coverage-driven verification, design automation, and continuous process improvement, you'll help deliver the quality and reliability that define Dolby's industry-leading cinema products.
Lead Software Engineer - Linux Infrastructure Platform JPMorgan Chase Bank, N.A.Lead Software Engineer - Linux Infrastructure PlatformSan Francisco, CAFull timeUsing AI to test and certify new Red Hat operating systems, create multiple image formats, and develop end-to-end automation capabilities using Ansible, Terraform, Jenkins, Bash, and Python, while exploring opportunities to learn and code with Python, Go, Rust and AI agents like Claude and Co-Pilot. As a Lead Software Engineer- Linux at JPMorgan Chase within the Corporate Sector Compute Infrastructure Platform (CIP) organization, you exhibit both depth and breadth of knowledge regarding software, applications, and technical processes across multiple technical disciplines.
Technology, Software Development Engineer In Test (Sdet), Vice President BTIG, LLCTechnology, Software Development Engineer In Test (Sdet), Vice PresidentSan Francisco, CA$110,000–$140,000 / yearExperience using AI-assisted development or test tools in terminal, CLI, or editor-based workflows (OpenCode, Claude Code, Codex, etc.); proven ability to critically review and correct agent-generated tests, commands, and code. The firm's core capabilities include global execution, portfolio, electronic and outsource trading, investment banking, prime brokerage, capital introduction, corporate access, research and strategy, commission management and more.