Silicon Photonics PIC Design Engineer Broadcom IncSilicon Photonics PIC Design EngineerSan Jose, CA$143,800–$230,000 / yearAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components that power our high-performance optical interconnect solutions.
Silicon Photonics PIC Design Engineer Broadcom CorporationSilicon Photonics PIC Design EngineerSan Jose, CA$143,800–$230,000 / yearAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. In this role, you will lead the design, simulation, layout, and system-level testing of advanced silicon photonics components that power our high-performance optical interconnect solutions.
Manufacturing Engineer, Powertrain and Electronics Joby AviationManufacturing Engineer, Powertrain and ElectronicsSan Carlos, California$98,400–$135,300 / yearFull timeDrive continuous improvement of existing production lines, processes, fixturing, tooling, and automated equipment, by applying Lean Manufacturing principles to reduce waste and improve safety, ergonomics, and material flow. Experience in one or more of the following fields: Electric motor assembly, complex mechanical assembly, electronics assembly, inverter assembly, cooling system assembly, or lithium-ion battery module/pack assembly.
NewManufacturing Engineer, Powertrain and Electronics Joby Aviation IncManufacturing Engineer, Powertrain and ElectronicsSan Carlos, CA$98,400–$135,300 / yearDrive continuous improvement of existing production lines, processes, fixturing, tooling, and automated equipment, by applying Lean Manufacturing principles to reduce waste and improve safety, ergonomics, and material flow. Experience in one or more of the following fields: Electric motor assembly, complex mechanical assembly, electronics assembly, inverter assembly, cooling system assembly, or lithium-ion battery module/pack assembly.
Materials Engineer NeuralinkMaterials EngineerSouth San Francisco, CA$113,000–$209,000 / yearOwn the in-house mechanical testing pipeline end-to-end: design fixtures, prepare specimens, run tests (servo-hydraulic, drop tower, DIC), and correlate results to simulation using quantitative metrics (CORA, force-displacement overlay, DIC contour comparison). This person will build explicit dynamics FEA models, design and run physical tests, calibrate material models against experimental data, and validate predictions.
Product Quality Engineer, GPU Platforms, Hardware Quality and Reliability Google LLCProduct Quality Engineer, GPU Platforms, Hardware Quality and ReliabilitySunnyvale, CAExperience leading cross-functional teams for continuous quality issue investigation and quality improvement using practical approaches (e.g., Six Sigma, Lean Manufacturing, Quality Metrics, DOE, SPC) and experience in technical leadership. The Global Hardware Quality and Reliability (GHQR) team is responsible for accelerating end-to-end product introduction and delivering predictable product quality and reliability, directly contributing to Google"s competitive advantage.
NewPCB Layout Engineer Danta TechnologiesPCB Layout EngineerMenlo Park, CA$50–$65 / hourAbility to deliver PCB CAD layout of High Density, High Speed memory designs (DDR5/LPDDR5), PCIe Gen 5 or Gen 6, Power Delivery, Mixed Analog/Digital. Collaborate with electrical engineers to review schematics and provide layout-driven feedback on component placement, power distribution network design, and signal routing strategies.
PCB Layout Engineer Pyramid Consulting, IncPCB Layout EngineerFremont, CA$55–$60 / hourAbility to deliver PCB CAD layout of High Density, High Speed memory designs (DDR5/LPDDR5), PCIe Gen 5 or Gen 6, Power Delivery, Mixed Analog/Digital. Perform high-speed digital layout for interfaces like HBM,DDR4/5, PCIe Gen 5/6, USB 3.2 or higher, with attention to controlled impedance, length matching, and crosstalk mitigation.
Lead Verification & Validation Engineer ALTEN Technology USALead Verification & Validation EngineerPalo Alto, CA$140,000–$175,000 / yearIn this role, you will play a critical role in ensuring the quality and reliability of our automotive systems — and serve as a technical lead across the V&V organization, guiding junior engineers and shaping validation strategy at the program level. We're ALTEN Technology USA, an engineering company helping clients bring groundbreaking ideas to life—from advancing space exploration and life-saving medical devices to building autonomous electric vehicles.
Lead Verification & Validation Engineer ALTEN TechnologyLead Verification & Validation EngineerPalo Alto, California$140,000–$175,000 / yearIn this role, you will play a critical role in ensuring the quality and reliability of our automotive systems — and serve as a technical lead across the V&V organization, guiding junior engineers and shaping validation strategy at the program level. We’re ALTEN Technology USA, an engineering company helping clients bring groundbreaking ideas to life—from advancing space exploration and life-saving medical devices to building autonomous electric vehicles.
UX Design Engineer, Content Tooling DoorDash IncUX Design Engineer, Content ToolingSunnyvale, CA$124,400–$183,000 / yearWe value a diverse workforce - people who identify as women, non-binary or gender non-conforming, LGBTQIA+, American Indian or Native Alaskan, Black or African American, Hispanic or Latinx, Native Hawaiian or Other Pacific Islander, differently-abled, caretakers and parents, and veterans are strongly encouraged to apply. You'll accelerate content design AI tooling so that CD's can focus on the highest leverage strategic work, while your tools enable product designers and cross functional partners to ship high-quality content faster across DoorDash, Wolt, and Deliveroo.
Top Level Physical Design Engineer TenstorrentTop Level Physical Design EngineerSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level.
RTL/Logic Design Engineer Advanced Micro Devices, IncRTL/Logic Design EngineerSanta Clara, CaliforniaWith experience in digital design, they bring expertise in high-speed memory interfaces such as HBM and GDDR and have a proven ability to deliver high-performance designs that meet timing, power, and area requirements. Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting HBM and GDDR DRAM Technologies.
Silicon Design Engineer Advanced Micro Devices IncSilicon Design EngineerSan Jose, CALead the end-to-end digital ASIC/SoC physical design cycle from RTL handoff through GDSII tapeout, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, signal integrity optimization, physical verification, and design signoff. ACADEMIC CREDENTIALS: Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor's degree and relevant industry experience is acceptable.
Senior ASIC Physical Design Engineer - San Jose, CA (100% Onsite) - FTE Permanent role - AS Central Business SolutionsSenior ASIC Physical Design Engineer - San Jose, CA (100% Onsite) - FTE Permanent role - ASSan Jose, CaliforniaClock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques. Minimum: Bachelor’s degree required in Electrical Engineering or Electronics Engineering.
Principal Analog Circuit Design Engineer - Serdes Intel Corp.Principal Analog Circuit Design Engineer - SerdesSanta Clara, CA$220,920–$311,890 / yearBusiness group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Job Details: Job Description: We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications.
SR ASIC SoC Design Engineer Advanced Micro Devices IncSR ASIC SoC Design EngineerSanta Clara, CAWe are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production. THE TEAM: Our group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generation AI networking workloads.
Senior FPGA Design Engineer Axiado CorpSenior FPGA Design EngineerSan Jose, CAAxiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Company's 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance's 2025 "Start-Up to Watch" award. We are a fastgrowing, wellfunded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AIdriven resilience and efficiency, and realtime platform management.
Principal Analog Circuit Design Engineer - SerDes Intel CorpPrincipal Analog Circuit Design Engineer - SerDesSanta Clara, CA$220,920–$311,890 / yearBusiness group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Job Details: Job Description: We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications.
Senior System Design Engineer NvidiaSenior System Design EngineerSanta Clara, CAIn this role, you will be working with peer system design engineers to develop NVIDIA GPU/Tegra based products for GPU cards, MGX servers, automotive, robotics, industrial PC, consumer electronics, etc. The base salary range is 168,000 USD - 258,750 USD for Level 4, and 200,000 USD - 322,000 USD for Level 5.