Mixed Signal Logic Design Engineer IntelMixed Signal Logic Design EngineerHillsboro, OregonJob Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). BS degree in Electrical Engineering or Computer Engineering or similar field of study with 4+ years relevant experience -OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 3+ years relevant experience.
NewModule Development Engineer - CMP IntelModule Development Engineer - CMPHillsboro, Oregon$133,800–$255,200 / yearBachelors degree in Materials Science, Chemical Engineering, Chemistry, Physics, Electrical Engineering, or a related Scientific STEM (Science Technology Engineering Math) field of study with 5+ years of Semiconductor Industry experience (semiconductor processing and semiconductor fabrication). Lead design and development of technically sophisticated manufacturing processes and/or repair reverse engineering including material selection, parameter optimization, equipment metrology, and system design to enable new product designs and functional requirements.
Silicon Packaging Design Engineer Intel Corp.Silicon Packaging Design EngineerHillsboro, OR$164,470–$232,190 / yearJob Details: Job Description: We are seeking an experienced Silicon Packaging Design Engineer with a strong background in board design and package-board integration to drive the end-to-end development of test boards supporting advanced silicon package validation and characterization. The ideal candidate will bring deep technical expertise in PCB design, signal integrity considerations, manufacturing requirements, and design rule compliance, along with a proven track record of delivering complex designs in high-volume semiconductor environments.
Maintenance/Engineering Midas HospitalityMaintenance/EngineeringHillsboro, ORYour day-to-day responsibilities will include performing routine inspections of equipment and facilities, addressing maintenance requests from staff and guests, and conducting preventative maintenance on hotel systems. As a new Maintenance team member at Midas Hospitality's Embassy Suites in Hillsboro, OR, you will engage in a variety of hands-on tasks to ensure the hotel operates smoothly.
Sales Engineer, Microscopy LumencorSales Engineer, MicroscopyNational Territory, ORThis position regularly interacts with Key Opinion Leaders (KOLs), namely imaging directors, core facility managers, principal investigators, influential microscopists, microscopy course directors, distributors, and OEM partners, to expand awareness and adoption of Lumencor illumination products. However, during the one year onboarding and territory development period, the Sales Engineer will receive substantial support from Lumencor's commercial organization, including sales leadership, marketing, technical support, customer service, and working directly with Lumencor’s Business Development Executive.
Analog and Mixed Signal Design Engineer IntelAnalog and Mixed Signal Design EngineerHillsboro, OregonJob Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Santa Clara Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. Experience in one or more of the following areas is preferred: GPIOs, high speed parallel or serial IO links and their subcomponents (data path, TX, RX, etc.), clock distribution, clock conditioning, clock recovery circuits, voltage regulators, voltage reference circuits, ADCs/DACs, inductors, transmission lines, RF and millimeter-wave circuits, test of custom analog and mixed-signal circuits.
Analog And Mixed Signal Design Engineer Intel Corp.Analog And Mixed Signal Design EngineerHillsboro, OR$164,470–$269,100 / yearPreferred Qualifications: Experience in one or more of the following areas is preferred: GPIOs, high speed parallel or serial IO links and their subcomponents (data path, TX, RX, etc.), clock distribution, clock conditioning, clock recovery circuits, voltage regulators, voltage reference circuits, ADCs/DACs, inductors, transmission lines, RF and millimeter-wave circuits, test of custom analog and mixed-signal circuits. Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly.
Electrical Engineer (6-Month Contract) Curtiss-WrightElectrical Engineer (6-Month Contract)Portland, Oregon$83,800–$95,000 / yearWilliams Controls Inc., a business unit of Curtiss-Wright manufactures products such as electronic, hydraulic and pneumatic throttle controls, configurable joysticks, adjustable pedal systems, sensors, hand controls and armrest systems for use on all types of commercial vehicles. Supports product reviews (both NPI and existing products) for Electromagnetic Compatibility (EMC), ensuring electronic equipment and systems can operate effectively in their intended applications.
Intel Process Integration Engineer - (Fe) Intel Corp.Intel Process Integration Engineer - (Fe)Hillsboro, OR$103,730–$198,820 / yearBenefits: We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative rewards that make Intel a Great Place to Work Find more information about our amazing benefits here. We provide benefits that promote a healthy, enjoyable life: excellent medical plans, wellness programs, and amenities, time off, recreational activities, discounts on various products and services, and many more creative perks that make Intel a Great Place to Work.
NewHydraulic Systems Engineer HYDRA-POWER SYSTEMS INCHydraulic Systems EngineerPortland, ORThe Systems Engineer is an individual contributor who is responsible for developing complete, engineered hydraulic solutions from sales descriptions and sketches, including hydraulic and electrical circuit design, mechanical design, and component selection. Displays excellent communication skills including presentation, persuasion, and negotiation skills required in working with customers and coworkers, including the ability to communicate effectively and remain calm and courteous under pressure.
Design Technology Tool Enablement Engineer IntelDesign Technology Tool Enablement EngineerHillsboro, Oregon$173,660–$284,580 / yearJob Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. As an EDA Tools Software Engineer, you will play a pivotal role in designing, developing, testing, and debugging software tools and flows that empower design teams to innovate faster and meet complex manufacturability requirements.
High speed PHY System Architect IntelHigh speed PHY System ArchitectHillsboro, California$164,470–$311,890 / yearJob Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Oregon, Hillsboro Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
High Speed PHY System Architect Intel Corp.High Speed PHY System ArchitectHillsboro, OR$164,470–$311,890 / yearBusiness group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Job Details: Job Description: Responsibilities will include but are not limited to: Develop and drive analog and mixed-signal IP architectures, signal processing algorithms, and calibration algorithms for system-on-chip (SoC) independent AMS IPs.
Senior Technologist, Hybrid Bonding Module Intel Corp.Senior Technologist, Hybrid Bonding ModuleHillsboro, OR$180,770–$255,200 / yearAdditional Locations: Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. As a Senior Technologist for Die-to-Wafer Hybrid Bonding (HBI), you will drive process and equipment development for next-generation hybrid bonding technologies, enabling Intel's leadership in advanced packaging for high-performance computing, AI, and chiplet architectures.
NewSenior CPU RTL Design Engineer Intel Corp.Senior CPU RTL Design EngineerHillsboro, OR$164,470–$311,890 / yearAs a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs. Technical Guidance: Provide technical leadership and support to the design team leadership including proposing creative, innovative methodology and process initiatives to consistently improve efficiency and quality.
Yield Development Engineer IntelYield Development EngineerHillsboro, OregonPreferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Experience listed below would be obtained through a combination of your schoolwork, classes, research and/or relevant previous job and/or internship experiences. Collaborating with cross-functional teams, you will develop methods and tools to analyze vast data sets, identify yield limiters, and implement process changes that enable Intel to achieve its yield milestones.
NewSenior CPU Front End Methodology Engineer Intel Corp.Senior CPU Front End Methodology EngineerHillsboro, OR$164,470–$311,890 / yearCPU RTL Methodology Engineer your responsibilities will include but are not limited to: Demonstrated leadership and hands-on experience in leveraging AI tools and methodologies to drive significant efficiency gains and improvements in RTL coding and other areas of silicon development. Develops and implements strategies, tools, and techniques for RTL development and logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as physical design integrity.
NewTait Radio Engineer BizTek People, Inc. | APA International Placement ConsultantsTait Radio EngineerPortland, ORConfiguration & Programming: Configure and program Tait radio equipment, including subscriber radios, base stations, and network controllers, using Tait software tools (e.g., Tait System Management, DMR Administrator, Enable Fleet). The ideal candidate will possess a deep understanding of Tait Communications products and technologies, with a proven track record in the design, installation, configuration, and troubleshooting of complex radio systems.
Cad/Eda Tools Automation Engineer Intel Corp.Cad/Eda Tools Automation EngineerHillsboro, OR$149,600–$245,160 / yearAdditional Locations: Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Senior Testchip SoC Physical Design Engineer (Integration & Methodology) IntelSenior Testchip SoC Physical Design Engineer (Integration & Methodology)Hillsboro, Oregon$141,910–$200,340 / yearThis team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness. Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips.