Principal Product Applications Engineer Astera LabsPrincipal Product Applications EngineerSan Jose, CA$165,000–$210,000 / yearYou will lead customer system design-in and Scorpio-related debug, develop customer-facing collateral, lead cross-functional Scorpio-related initiatives, and drive and validate new features across PCIe Gen 6 / Gen 7 & UALink platforms - directly influencing the roadmap of a hyper-growth company powering the next generation of AI compute. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Board Design Engineer Array LabsBoard Design EngineerRedwood City, CaliforniaTo conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Hands-on experience laying out high-performance platforms including compute (SoCs, FPGAs, MCUs), storage (DDR, SSDs), high-speed interfaces (PCIe, SPI, JESD204B), RF components (PAs, LNAs, switches).
Performance Engineer Astera LabsPerformance EngineerSan Jose, CA$135,000–$170,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Our Scorpio scale-up fabric switches are purpose-built to unlock the performance of next-generation AI workloads, and we're looking for a Senior Performance Engineer to demonstrate the real-world value of our silicon where it matters most: on real inference and training workloads running on GPUs at scale.
Principal Board Product Engineer MarvellPrincipal Board Product EngineerSanta Clara, CAHighlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. This role will serve as the technical bridge between ASIC development, hardware design, manufacturing, test engineering, compliance, suppliers, and operations teams to ensure successful product launches.
Principal Engineer - Item Master MarvellPrincipal Engineer - Item MasterSanta Clara, CAHighlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. The Product Lifecycle Management (PLM) Principal Engineer is responsible for overseeing and optimizing the end-to-end lifecycle of a product-from concept and development through production, launch, support, and retirement.
Principal Product Engineer - Networking & Connectivity MarvellPrincipal Product Engineer - Networking & ConnectivitySanta Clara, CAThe team operates across multiple business units and works closely with design engineering, operations, program management, quality, and leadership to guide technologies from early development into production ready silicon. Master's degree and/or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 5+ years of relevant industry experience, preferably in semiconductors.
Fabric Modeling And Analysis Engineer For Scale Up Fabric Astera LabsFabric Modeling And Analysis Engineer For Scale Up FabricSan Jose, CA$185,000–$240,000 / yearServe as the internal authority on fabric modeling, partnering with ASIC architects and product teams to drive roadmap and feature decisions, support early customer engagement, and produce modeling reports, white papers, and presentations for engineering, product, and executive audiences. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Engineering Technician Manpower EngineeringEngineering TechnicianFoster City, CATemporaryManpowerGroup® (NYSE: MAN), the leading global workforce solutions company, helps organizations transform in a fast-changing world of work by sourcing, assessing, developing, and managing the talent that enables them to win. We are recognized consistently for our diversity - as a best place to work for Women, Inclusion, Equality and Disability and in 2023 ManpowerGroup was named one of the World's Most Ethical Companies for the 14th year - all confirming our position as the brand of choice for in-demand talent.
HW Development Engineer Anritsu CoHW Development EngineerMorgan Hill, CA$180,000–$240,000 / yearAnritsu engages customers as true partners to help develop wireless, optical, microwave/RF, and digital solutions for R&D, manufacturing, installation, and maintenance applications, as well as multidimensional service assurance solutions for network monitoring and optimization. The company develops advanced solutions for emerging and legacy wireline and wireless technologies used in commercial, private, military/aerospace, government, and other markets.
Product Integration, Senior Principal - Active Electric Cable / Smart Cable Module Business Astera LabsProduct Integration, Senior Principal - Active Electric Cable / Smart Cable Module BusinessSan Jose, CAAs our product portfolio expands in complexity, performance, and volume - and as OEM customers increasingly adopt Astera Labs silicon into their own designs - we need a senior engineering leader to build and scale the hardware design engineering organization that creates industry-defining products and enables our customers' success. This is a deeply technical, hands-on individual contributor role at the most senior level - responsible for ensuring that every element of an AEC product (silicon, firmware, PCB/substrate, cable assembly, connector, mechanical, thermal, and signal integrity) comes together into a fully validated, production-ready, customer-qualified product.
Software Engineering Intern, Power Modeling & AI Tools Tenstorrent UniversitySoftware Engineering Intern, Power Modeling & AI ToolsSanta Clara, CaliforniaYour work will include integrating and analyzing engineering data, developing internal tools and scripts, creating visualizations and AI-enabled interfaces, and supporting workload profiling, model validation, and analytics to improve power model accuracy and reliability. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
Principle Validation And Hardware Design Engineer MarvellPrinciple Validation And Hardware Design EngineerSanta Clara, CAMarvell, a high-speed analog/mixed-signal semiconductor company, is the market leader in high-speed and optical interconnects for communication infrastructure in long-haul, metro and datacenter. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Principal Serdes Bring-Up Validation Engineer Astera LabsPrincipal Serdes Bring-Up Validation EngineerSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization), with the ability to investigate jitter sources, CDR/PLL behavior, crosstalk, and power integrity issues.
Analog IC Layout Engineer NeuralinkAnalog IC Layout EngineerSouth San Francisco, CA$83,000–$139,000 / yearJob Description and Responsibilities: We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces.
Senior Staff Post-Silicon Validation Engineer MarvellSenior Staff Post-Silicon Validation EngineerSanta Clara, CAPurpose-built to scale data center compute fabrics inside accelerated servers, general-purpose servers, CXL systems and disaggregated infrastructure, the Alaska P PCIe retimer line features best-in-class SerDes performance, ultra-low power dissipation, low latency, and a rich feature set including advanced diagnostics and telemetry. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Staff Engineer, HIL Design, Hardware Integration & Test Cariad, Inc.Staff Engineer, HIL Design, Hardware Integration & TestMountain View, CA$161,710–$234,325 / yearThe Staff Engineer, HIL Design, Hardware Integration & Test owns the hardware-oriented architecture, build, bring-up, and sustained readiness of HIL benches, integration benches, harnesses, Interface Control Documents (ICDs), and AI-enabled lab automation used to validate CARIAD, Inc. hardware platforms. Hands-on integration and debug of display interfaces, analog audio, digital audio, RF/radio communication paths, CAN/CAN FD, LIN, Ethernet/1000BASE-T1, serial, USB, UART, SPI, I2C, GPIO, analog/digital I/O, power/wake lines, and diagnostics.
L3 IT Service Desk Engineer ZonesL3 IT Service Desk EngineerSan Jose, CAFull timeOperating in more than 120 countries, leveraging a robust portfolio, and utilizing the highest certification levels from key partners, including Microsoft, Apple, Cisco, Lenovo, Adobe, and more, Zones has mastered the science of building digital infrastructures that change the way business does business ensuring whatever they need, they can Consider IT Done. Position Overview: Term: 6-month contract to hire Location: on-site in San Jose California Pay: up to $39/hr Hours: M-F- 8-5pm What you will do as the L3 IT Service Desk Engineer: You will help provide technical information to education and service teams,and may assist with teaching and presenting technical hardware/software to many audiences.
Optical Test Engineer, Principal Astera LabsOptical Test Engineer, PrincipalSan Jose, CA$185,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. This senior role drives optical and electro-optical testing for next-generation high-bandwidth CPO modules and optical engines integrated with ASICs for AI, hyperscale data centers, and high-performance computing.
Opto-Mechanical Engineer AetherfluxOpto-Mechanical EngineerSan Carlos, CaliforniaMechanical Integration: Work closely with the mechanical engineering team to design and integrate opto-mechanical systems for satellite platforms, ensuring that optical components can withstand the rigors of space. Laser System Design & Integration: Design and model laser systems, including solid-state, fiber, or semiconductor lasers, and integrate them with mechanical structures for space deployment.
Controls Engineer Mind RoboticsControls EngineerPalo Alto, CaliforniaWe believe the hardest problems in AI are solved when researchers and engineers are hands-on with the physical world every day - and we're looking for people who are passionate about robotics, value ownership, and are excited to tackle difficult problems. We're looking for a Controls Engineer to own the algorithms and software that make our robots move well — from low-level actuator loop design to full-body motion control and the simulation infrastructure that keeps us iterating fast.