Work closely with silicon engineering teams to coordinate high-level milestones for IP development and integration Ability to multi-task and manage IPs across several projects simultaneously Drive resolution of technical and post-silicon issues between cross-functional teams and external IP providers Planning and tracking silicon validation schedule, testplan reviews and spec signoff with cross-functional teams Coordinate weekly meetings with vendors and IP consumers to resolve technical/schedule issues Assemble regular project status presentations for cross-functional executive reviews Focused issue reporting, bug tracking and communication of program risks and status Identify risks, develop mitigation strategies, and facilitate conflict resolutionBS in engineering field and 10 + years of experience in Analog/Digital Circuit Design or working with Analog and/or Digital IP integration in ASIC/SOC/VLSI Designs or similar experience Strong knowledge of the IP development process, tools/flows and methodologies, silicon validation of the IP and the life cycle in a SOCAdvanced skills in Technical Program or Project Management, or Functional Management experience Strong team player and creative thinker who can lead technical teams, cross-functional groups, and vendors to meet aggressive development schedules Experience working with IP vendors or IP providers Great leadership and communication skills (Executive communication) Experience working in a dynamic engineering environment, strong at multi-tasking, conflict resolution and real-time crisis management Post Silicon Debug skills Driven, motivated and comfortable with fast paced schedule driven environment Ready to participate in technical discussions, ask probing questions, and work with the team to pull together scoping, schedules, and solutions to issues. This role will focus on cross-functional communication working directly with Apple engineering teams, operations, legal, and 3rd party vendors to coordinate releases and drive, track and resolve issues associated with 3rd party IP development, design integration and silicon validation of the IP.