Sr Principal Engineer, Enclosures Design BloomEnergySr Principal Engineer, Enclosures DesignSan Jose, CA$196,000–$282,000They have experience in the automotive industry having delivered cars and trucks to the vehicle marketplace, or in NEMA 4X compliant enclosures, sealing strategies and manufacturing approaches that survive real world deployment for decades. Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm.
Principal Engineer, Product Compliance BloomEnergyPrincipal Engineer, Product ComplianceSan Jose, CA$176,300–$253,700Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm. For over two decades, we’ve been at the forefront of the global energy transition, pioneering solutions that empower critical industries to thrive in a rapidly digitizing, energy-intensive world.
Principal Engineer - Standard Cell Design Intel Corp.Principal Engineer - Standard Cell DesignSanta Clara, CA$220,920–$311,890 / yearBusiness group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Principal Electrical Engineer - (99105.1) SanminaPrincipal Electrical Engineer - (99105.1)San Jose, CA$150,000–$200,000 / yearThe total rewards package also includes a variety of benefits, including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business and, depending on the role, may include eligibility for restricted stock unit awards and participation in a discretionary bonus program. VES also designs and builds NVMe flash based server appliances, JBOD storage systems and related products for a variety of data center and storage applications.
Principal Engineer, Signal-Integrity and Power-Integrity SK hynix AmericaPrincipal Engineer, Signal-Integrity and Power-IntegritySan Jose, California$185,000–$220,000 / yearMethodology Development: Invent and propagate best‑practice SIPI methodologies, including electromagnetic extraction, multi‑port S‑parameter modeling, and power‑network analysis for complex packaging environments. Architecture & Design: Lead the creation of high‑performance SiP architectures (HBM, interposer, 3 D stacks) and validate power‑delivery and signal‑integrity across the full stack—from silicon to substrate.
Principal Electrical Engineer, NPI BloomEnergyPrincipal Electrical Engineer, NPIFremont, CA$176,300–$253,700Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm. For over two decades, we’ve been at the forefront of the global energy transition, pioneering solutions that empower critical industries to thrive in a rapidly digitizing, energy-intensive world.
Principal Engineer, SerDes AMS Design and Architecture Ayar LabsPrincipal Engineer, SerDes AMS Design and ArchitectureSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Key Responsibilities: Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
Principal Engineer, AI System Architect (Hardware) Samsung SemiconductorPrincipal Engineer, AI System Architect (Hardware)San Jose, CA$219,000–$351,000 / yearAnalyze representative and emerging system-level architectural research (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung's long-term AI platform strategy.
Principal Engineer, Electronic Hardware Design Ayar LabsPrincipal Engineer, Electronic Hardware DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Principal Engineer, SerDes Validation Ayar LabsPrincipal Engineer, SerDes ValidationSan Jose, CaliforniaDrive Product Bring-up: Collaborate with Design Engineering to bring up cutting-edge silicon photonic and laser products, troubleshooting and resolving complex technical issues on the optical SerDes devices. Lead New Product Introduction (NPI): Collaborate with multi-disciplinary teams to identify and implement product improvements through bench characterization and ensure successful transition of products from development to mass production.
NewSr Principal Engineer -Sipi CadenceSr Principal Engineer -SipiSan Jose, CA$154,000–$286,000 / yearWork on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models. Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders.
Principal Engineer, SOC Design Samsung SemiconductorPrincipal Engineer, SOC DesignSan Jose, CA$219,000–$351,000 / yearBachelors in Electrical, Computer Science or related with 20+ years of experience or Masters in Electrical, Computer Science or related Science with 18+ years of Industry Experience or PhD in Electrical, Computer Science or related Science with 15+ years of Industry experience preferred. Come join the team that is creating new computing system architectures needed to support emerging machine learning applications, data analytics and edge computing.
Principal Engineer, AI Tooling And Workflows NvidiaPrincipal Engineer, AI Tooling And WorkflowsSanta Clara, CAIn this role, you will define and build agentic AI systems, developer productivity platforms, and intelligent workflow automation that accelerate software delivery across NVIDIA's engineering organization. Partner with engineering leaders, teams across products, infrastructure, security, and research to identify high-leverage opportunities and deliver solutions with broad impact.
NewSenior Principal Engineer (Board & System Hardware Design AI & Cloud Infrastructure) Macpower Digital Assets Edge Private LimitedSenior Principal Engineer (Board & System Hardware Design AI & Cloud Infrastructure)Santa Clara, CA$200,000–$266,400 / yearYou will spend most of your time reviewing and shaping customer hardware designs covering board architecture, PCB stack-up and material selection, power architecture, thermal design, mechanical integration, and reliability and retain full hands-on capability across the entire design lifecycle from architecture through schematic, layout guidance, and bring-up. Job Summary: As Senior Principal Engineer (Board & System Hardware Design AI & Cloud Infrastructure), you will be the senior technical authority guiding customer hardware design-in on the Ethernet Switch and UALink platforms, and a key technical bridge between the silicon teams, internal hardware engineering, and the field.
NewSenior Principal Engineer, Hardware Application Engineering (SI/PI) 112G/224G SerDes Macpower Digital Assets Edge Private LimitedSenior Principal Engineer, Hardware Application Engineering (SI/PI) 112G/224G SerDesSanta Clara, CA$195,000–$266,400 / yearWhat You Can Expect As a Senior Principal Engineer, Hardware Application Engineering (SI/PI) 112G/224G SerDes you will be the senior technical authority responsible for ensuring that customer platforms built on our Ethernet Switch and UALink silicon meet the highest performance and quality threshold from first prototype through mass-production deployment. You will own layout guideline definition, post-silicon channel extraction and simulation, compliance testing, and SerDes tuning guidance, while also reviewing customer PDN designs and feeding learnings back to our silicon and hardware engineering teams as part of a continuous improvement loop.
Sr Principal Engineer, Application Engineering & System Design Fox Point Recruitment LLCSr Principal Engineer, Application Engineering & System DesignSanta Clara, CA$200,000–$266,400 / yearYour primary mission is to ensure that customers’ next-generation switches, AI fabric platforms, and networking systems are designed right the first time—performant, manufacturable, reliable, and ready for high-volume production. Develop and deliver high-impact technical training to customers and internal teams covering proprietary silicon, reference designs, high-speed design best practices, and productization methodologies.
Senior Principal Engineer -Hardware Signal Integrity & Power Integrity Fox Point Recruitment LLCSenior Principal Engineer -Hardware Signal Integrity & Power IntegritySanta Clara, CA$199,800–$266,400 / yearAs the Senior Principal Engineer for Signal Integrity (SI) and Power Integrity (PI) , you will serve as the senior technical authority responsible for ensuring that customer platforms built on our Ethernet Switch and UALink silicon meet the highest performance and quality thresholds — from first prototype through mass-production deployment. Compliance & Lab Debug: Lead lab characterization and compliance testing (BER/SER, eye-opening margins, jitter, return loss, crosstalk) using VNAs, BERTs, scopes, TDR, and jitter analyzers.
Principal Engineer, Mapping and Localization PlusAIPrincipal Engineer, Mapping and LocalizationSanta Clara, CADesign and implement robust, real-time algorithms for sensor fusion, visual/LiDAR odometry, and global localization using techniques like Factor Graphs, EKF/UKF, and particle filters. You will tackle the hardest edge cases—from GPS-denied tunnels to dynamic construction zones—ensuring our vehicles operate safely in complex L4 ODDs (Operational Design Domains).
Sr. Principal Electrical Engineer, Microgrid Modeling Bloom EnergySr. Principal Electrical Engineer, Microgrid ModelingSan Jose, CaliforniaThis position is intended for an engineer with deep domain expertise and extensive hands‑on experience in microgrid modeling and simulation, capable of independently evaluating complex systems and operating scenarios and delivering high‑confidence, model‑driven insights to support system design and validation. This role focuses on advanced electrical and dynamic modeling of inverter‑based resources, energy storage systems, generation assets, microgrid controllers, and distribution networks to ensure robust performance, stability, resilience, and compliance with project requirements and applicable grid codes.
Principal Engineer, Signal-Integrity And Power-Integrity SK hynixPrincipal Engineer, Signal-Integrity And Power-IntegritySan Jose, CA$185,000–$220,000 / yearMethodology Development: Invent and propagate best‑practice SIPI methodologies, including electromagnetic extraction, multi‑port S‑parameter modeling, and power‑network analysis for complex packaging environments. Architecture & Design: Lead the creation of high‑performance SiP architectures (HBM, interposer, 3 D stacks) and validate power‑delivery and signal‑integrity across the full stack-from silicon to substrate.