Own the verification of custom RTL blocks, subsystems, and full FPGA-level functionality\n Work with RTL design engineers and system architects to define verification plans based on system specifications, design goals, and use cases\n Develop and maintain verification environment in SystemVerilog/UVM including constrained-random, directed, and system-level testbenches\n Develop and maintain stimulus generators, drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces\n Work closely with RTL design engineers to triage and resolve bugs, owning and driving technical issues to resolution\n Collect and report code and functional coverage\n* Maintain regular simulation regressions\n\n. For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $144,500.00- $216,500.00/ annually \n \nAt Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience.