Director of Design (UI/UX + Brand) GantriDirector of Design (UI/UX + Brand)San Francisco, CAWe’re looking for a Director of Design to lead brand design, UI/UX, and creative at Gantri — someone with exceptional taste and a track record of building cohesive, elevated brand experiences for design-forward, tech-enabled consumer companies. Lead the UI/UX vision for gantri.com , MadeOS (our custom manufacturing platform) and our industry-leading FactoryOS software, ensuring the digital experience reflects the quality and intentionality of our brand.
VP, Product Design, Informatica Tableau SoftwareVP, Product Design, InformaticaRedwood City, CADevelop and articulate a compelling design vision shaped by design thinking principles — emphasizing empathy, ideation, prototyping, and testing — and use experience, credibility, and strategic insight to inspire bold ideas and drive transformative outcomes across the organization and broader Salesforce ecosystem. Strategic Vision & Leadership: • Build a culture of customer obsession by embedding it into every facet of design strategy — championing a deep understanding of real user problems and fostering innovation and customer-centered thinking across the team.
Design Verification Engineer Broadcom CorporationDesign Verification EngineerSan Jose, CA$120,000–$192,000 / year2) Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems. 3) Developing verification environments including testbenches and verification API's associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains.
Analog/Mixed Signal Verilog Modeling Design Engineer Broadcom CorporationAnalog/Mixed Signal Verilog Modeling Design EngineerSan Jose, CAJob Description: Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
Design Engineer - Flow Development Broadcom CorporationDesign Engineer - Flow DevelopmentSan Jose, CAThe candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. Our group's mission is to provide an advanced timing sign-off flow to Broadcom's chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins.
Nvidia 2027 Internships: Hardware Design For Test (Dft) NvidiaNvidia 2027 Internships: Hardware Design For Test (Dft)Santa Clara, CACourse or internship experience related to the following areas could be required: Design for Test (DFT), Digital Design, Test Architecture and DFT Planning, Static Timing Analysis (STA), Pre-Silicon and Post-Silicon Issue Debug. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society - from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create.
Design Engineer - Flow Development Broadcom IncDesign Engineer - Flow DevelopmentSan Jose, CAThe candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. Our group's mission is to provide an advanced timing sign-off flow to Broadcom's chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins.
NVIDIA 2027 Internships: Hardware Design for Test (DFT) NVIDIA CorpNVIDIA 2027 Internships: Hardware Design for Test (DFT)Santa Clara, CACourse or internship experience related to the following areas could be required: Design for Test (DFT), Digital Design, Test Architecture and DFT Planning, Static Timing Analysis (STA), Pre-Silicon and Post-Silicon Issue Debug. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society - from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create.
Senior Digital Design Engineer NVIDIA CorpSenior Digital Design EngineerSanta Clara, CAWhat you'll be doing: As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks. We have some of the most forward-thinking and hardworking people in the world working for us, and, due to outstanding growth, our special engineering teams are growing fast.
Digital Design Verification Engineer Broadcom CorporationDigital Design Verification EngineerSan Jose, CAAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. Job Description: The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs.
Digital Design Engineer E-SpaceDigital Design EngineerSaratoga, CAOur team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
Digital Design Specialist: Structural Engineering LPADigital Design Specialist: Structural EngineeringSan Jose, CaliforniaLPA’s structural engineers have been repeatedly recognized by our peers in the structural engineering community for our innovative and technically challenging designs, including receiving SEAOC’s Excellence in Structural Engineering and People’s Choice Award in 2021 along with multiple national engineering awards from NCSEA and AISC. Opportunities to propose and lead projects that impact your local community, including more than $1 million since 2015 in Habitat for Humanity builds, scholarships, and other pro bono community projects.
Creative Director, Design Meta Platforms IncCreative Director, DesignBurlingame, CAYou will partner with product designers, content designers, industrial designers, motion designers, creative technologists, and engineers to ship high-quality digital retail experiences for our expanding hardware portfolio. We have developed best-in-class collaboration models with agencies and our cross-company creative network to ensure a consistent and effective creative narrative for work that reaches an audience across the globe due to the scale of our products.
Staff ASIC Design Verification Engineer Google LLCStaff ASIC Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Were the driving force behind Googles groundbreaking innovations empowering the development of our cutting-edge AI models delivering unparalleled computing power to global services and providing the essential platforms that enable developers to build the future.
Senior Hardware Design Engineer SambaNova Systems, Inc.Senior Hardware Design EngineerSan Jose, CA$120,000–$200,000 / yearIn this role you will take ownership of blocks within a larger subsystem - contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tapeout, and silicon bring-up. SambaNova Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs deployed in our AI workload acceleration systems.
Sr. RTL Design Engineer RivianSr. RTL Design EngineerPalo Alto, CaliforniaFull timeRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services.
Senior Engineer, GPU RTL Design Samsung Electronics America IncSenior Engineer, GPU RTL DesignSan Jose, CA$124,000–$208,400 / yearAs an Engineer or Senior or Staff GPU RTL Design Engineer, you will contribute to the design and development of complex RTL blocks and subsystems for Samsung's next-generation mobile GPU IPs, delivering high-quality, scalable implementations that power premium smartphones and adjacent consumer technologies. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world.
PMTS ASIC Digital Design IP ENGINEERING GlobalFoundries IncPMTS ASIC Digital Design IP ENGINEERINGSanta Clara, CA$167,000–$275,000 / yearSummary of Role: The PMTS Digital Design Engineer will lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies.
Design Director (Innovation & Engineering) Turner & TownsendDesign Director (Innovation & Engineering)San Francisco, CA$150,000–$200,000 / yearThis individual will serve as a subject matter expert within the Innovation & Engineering team, partnering closely with the Vice President of Architecture to guide BOD and BTS design activities, oversee third‑party consultants, and ensure project documentation is accurate, timely, and within budget. The successful candidate will be a driven leader with strong technical expertise, excellent communication skills, and the ability to influence design strategy across a complex and fast‑growing portfolio.
SoC Design Lead TYLsemiSoC Design LeadSan Jose, CaliforniaFront-End Signoff Discipline: Ensure quality and signoff readiness across the front-end using static verification tools (Linting, Clock Domain Crossing/CDC, Reset Domain Crossing/RDC, and Logical Equivalence Checking/LEC). AI-Driven Design Automation: Evaluate, pilot, and deploy AI-powered design assistants and LLM copilots within the RTL generation, code review, and documentation workflows to accelerate design velocity.