Sr. Computer Graphics Engineer RyloSr. Computer Graphics EngineerSan Francisco, CADeveloped by a team of former Instagram and Apple engineers, Rylo’s breakthrough stabilization software and smartphone app eliminate the traditional pain points of shooting, editing, and sharing videos. Experience working on render architecture with modern graphics APIs (Vulkan, Metal, D3D12), extra credit if the engine was multithreaded.
Civil Engineer, Structural focus Kennedy/Jenks Consultants IncCivil Engineer, Structural focusSanta Clara, CA$113,000–$170,000 / yearThis role supports the integrity, life safety, constructability, and long-term performance of facilities such as pump stations, reservoirs, treatment plant buildings, tanks, clarifiers, and related infrastructure while working closely with engineers, designers, and construction teams as part of the Kennedy Jenks Technical Services Team. KJ is at the forefront of developing sustainable solutions for clients, including green infrastructure design, strategies to reduce energy use and environmental impacts, award-winning water reuse projects, and efficient construction management practices that ensure quality, safety, and on-time delivery.
Sr. Staff Engineer, ASIC Design Ayar LabsSr. Staff Engineer, ASIC DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
PCB Design Layout Engineer NVIDIA CorpPCB Design Layout EngineerSanta Clara, CAWhat you'll be doing: Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value-conscious PCBs for all business units at NVIDIA (Data Center, GPU Desktop, Notebook, Automotive, Professional, Deep Learning, and AI). We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing.
PD - Sr Staff - CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology | Eliyan CorporationPD - Sr Staff - CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |CALead methodology and execution for low-power core design targeting aggressive PPA targets in accelerator product lines covering power intent definition, multi-voltage domain management, and clock gating strategy. Define and own comprehensive clocking methodology covering Clock Mesh, Spine-and-Rib, H-Tree, and hybrid topologies selecting the optimal strategy per design class, frequency target, and power budget.
Senior Design Verification Engineer Google LLCSenior Design Verification EngineerMountain View, CAApplyshare linkCopy linkemailEmail a friendMinimum qualificationsBachelors degree in Electrical Engineering Computer Engineering Computer Science a related field or equivalent practical experience.8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience with different verification techniques and methodologies including formal GLS UPF based Power simulations UVM and C based testing etc. to achieve bug-free Silicon in complex SoCs.
Senior RTL Design Engineer MythicSenior RTL Design EngineerPalo Alto, CA$120,000–$225,000 / yearWe've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. Because today's AI workloads push the limits of performance, memory, and efficiency, our RTL engineers apply both creativity and rigor to deliver designs that meet aggressive PPA (performance, power, area) goals while ensuring correctness.
RTL Design Engineer MythicRTL Design EngineerPalo Alto, CA$120,000–$225,000 / yearWe're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
Machine Learning Digital Design Engineer Meta Platforms IncMachine Learning Digital Design EngineerSunnyvale, CAContribute to ASIC digital µArchitecture and design Assist performance/power analysis of the design and help meet power and performance targets Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test Develop micro-architecture, RTL coding, and design verification for complex IPs Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leadsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of experience as a Hardware Design Engineer for production silicon shipped in volume Experience in digital design µArchitecture, RTL coding, and micro-architecture development Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams Experience in ML accelerator subsystems and top level design Experience in SoC integration and ASIC architecture Knowledge of microcontrollers, DSP, CDC and power sequence Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements) Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews) Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologiesMeta builds technologies that help people connect, find communities, and grow businesses. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.
Sr Mgr/Dep Director ASIC Digital Design IP ENGINEERING GlobalFoundries IncSr Mgr/Dep Director ASIC Digital Design IP ENGINEERINGSanta Clara, CA$167,000–$275,000 / yearThis role provides technical and organizational leadership for a team of digital design engineers, driving architecture implementation, RTL development, integration, verification closure support, and successful silicon execution. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies.
Senior ASIC Design Verification Engineer, Google Cloud Google LLCSenior ASIC Design Verification Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewASIC Design Verification Manager, TPU Compute Google LLCASIC Design Verification Manager, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Lead the functional verification team for significant portions of TPU Compute team, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing advanced functional verification infrastructure such as subchip, subsystem, and fullchip level environments.
NewRTL Design Engineer, TPU Google LLCRTL Design Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Design Engineer - Flow Development Broadcom IncDesign Engineer - Flow DevelopmentSan Jose, CAThe candidate must have the ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on-time, work well with external and internal partners, and possess advanced IC design engineering skills. Our group's mission is to provide an advanced timing sign-off flow to Broadcom's chip teams with the goal of achieving best in class solutions with high yield and fully optimized margins.
NVIDIA 2027 Internships: Hardware Design for Test (DFT) NVIDIA CorpNVIDIA 2027 Internships: Hardware Design for Test (DFT)Santa Clara, CACourse or internship experience related to the following areas could be required: Design for Test (DFT), Digital Design, Test Architecture and DFT Planning, Static Timing Analysis (STA), Pre-Silicon and Post-Silicon Issue Debug. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society - from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create.
Senior Digital Design Engineer NVIDIA CorpSenior Digital Design EngineerSanta Clara, CAWhat you'll be doing: As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks. We have some of the most forward-thinking and hardworking people in the world working for us, and, due to outstanding growth, our special engineering teams are growing fast.
Analog/Mixed Signal Verilog Modeling Design Engineer Broadcom CorporationAnalog/Mixed Signal Verilog Modeling Design EngineerSan Jose, CAJob Description: Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
Digital Design Verification Engineer Broadcom CorporationDigital Design Verification EngineerSan Jose, CAAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. Job Description: The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs.
Graphics Cache Hierarchy Design Verification Engineer Apple IncGraphics Cache Hierarchy Design Verification EngineerSanta Clara, CAThe Graphics Cache Hierarchy Verification Engineer will be responsible for the pre-silicon RTL verification of graphics memory subsystem units including Caches, Memory Management Unit, Interconnects and Link interface units. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.
Design Verification Engineer (Silicon Engineering) SpaceXDesign Verification Engineer (Silicon Engineering)Palo Alto, CA$135,000–$155,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.