Senior Front End Design Engineer (Microarchitecture) Cerebras SystemsSenior Front End Design Engineer (Microarchitecture)Sunnyvale, CA$250,000–$300,000 / yearYou will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
Instructional Designer - Field & Operations (Temp) ACCO Engineered Systems IncInstructional Designer - Field & Operations (Temp)Pleasanton, CA$65,000–$88,750 / yearApplicants please note that actual compensation is determined by several factors that are unique to each candidate, including but not limited to job-related skills, depth of experience, certifications, relevant education or training, and specific work location, among others. Apply solid instructional design skills, effective learning principles, and creativity to course design to engage employees in the learning process, encourage participation, and meet the requirements of the adult learner.
Senior Director Analog IC Design Lattice Semiconductor CorpSenior Director Analog IC DesignSan Jose, CaliforniaProven design experience in most of the following analog, mixed-signal circuits: SerDes receivers/transmitters, low-jitter PLLs, oscillators, phase interpolators, ADC/DAC, high speed clock distribution, bandgap/bias, and voltage regulators. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry.
Design Verification Engineer - Soc Etched AIDesign Verification Engineer - SocSan Jose, CABacked by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads.
New3D Design Teaching Opportunities (Tinkercad) Concorde Education3D Design Teaching Opportunities (Tinkercad)San Mateo, California$50–$100 / hourPreferred qualifications include: • At least 60 college credits, where required by the applicable assignment or site; • Experience with Tinkercad or similar 3D design, CAD, modeling, engineering, architecture, fabrication, or digital design tools; • Experience teaching, tutoring, coaching, mentoring, or leading activities with school-age students; • Strong communication, organization, and classroom facilitation skills; • Availability to provide services for the accepted assignment schedule and communicate schedule issues as soon as reasonably practicable; and. Assignments may include topics such as: • Creating, resizing, and manipulating 3D shapes and objects; • Aligning, grouping, and combining design elements; • Designing with measurements, scale, and precision; • Basic design-thinking and prototyping concepts; • Building 3D models using Tinkercad or similar design platforms; • Exporting digital models and preparing designs for 3D printing, where applicable; and.
NewDesign Engineer III MindlanceDesign Engineer IIISunnyvale, CA$80–$87 / hourPerform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams. Day-to-day: build/run testbenches and regressions, analyze coverage, debug failures, and measure power/performance with the design team; work daily with 2 3 teammates and other CWs.
Physical Design Lead, ASIC Google LLCPhysical Design Lead, ASICSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff.
Design Technology Co-Optimization Engineer Google LLCDesign Technology Co-Optimization EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Principal Mixed Signal RTL Design Engineer TYLsemiPrincipal Mixed Signal RTL Design EngineerSan Jose, CaliforniaDesign and implement supporting digital blocks: ADC interface, DPWM (digital PWM), Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting. Prior experience designing digital controllers for integrated voltage regulators (IVRs) , point-of-load (PoL) converters, or high-current AI/HPC power delivery.
Sr. Design Verification Engineer Credo Semiconductor, Inc.Sr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Design Verification Lead Advanced Micro Devices, IncDesign Verification LeadSan Jose, CaliforniaAs a member of the front-end design and integration team, you will collaborate closely with architecture, IP design, physical design, firmware, and product engineering teams to deliver first-pass silicon success for next-generation PCIe and CXL-based IP solutions. KEY RESPONSIBILITIES: Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
SOC Physical Design Static Timing Analysis Engineer Intel Corp.SOC Physical Design Static Timing Analysis EngineerSanta Clara, CA$164,470–$311,890 / yearJob Details: Job Description: As a Physical Design Timing Engineer, you will play a pivotal role in shaping the performance, power efficiency, and functionality of Intel's cutting-edge System-on-Chip (SoC) designs. Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
Lead Analog Serdes Architect/Design Engineer Intel Corp.Lead Analog Serdes Architect/Design EngineerSanta Clara, CA$220,920–$311,890 / yearThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership.
Adjunct Professor - Design Program University of San FranciscoAdjunct Professor - Design ProgramSan Francisco, CAJob Summary: The Design Program, inside the Department of Art + Architecture at the University of San Francisco, invites applications for a pool of qualified, temporary, part-time instructors to teach on-site, in-person classes for our Design Program. Ideal candidates connect design practice to issues of political, environmental, and community concern, and are conversant with historical and contemporary issues in the field.
Senior ASIC Design Engineer - Agentic AI NVIDIA CorpSenior ASIC Design Engineer - Agentic AISanta Clara, CAWhat you'll be doing: As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
Sr. Design Verification Engineer DustPhotonics LtdSr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Senior FPGA Design Engineer (MTD, San Jose, CA) Teradyne IncSenior FPGA Design Engineer (MTD, San Jose, CA)San Jose, CA$170,400–$272,600 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
RTL Design Engineer, Interconnect & Memory Systems Tesla IncRTL Design Engineer, Interconnect & Memory SystemsPalo Alto, CA$128,000–$414,000 / yearIn this role, you will focus on the critical data path elements of custom ASICs, including Network on Chip (NoC) architectures, DMA engines, memory controllers, Memory Management Units (MMUs), arbiters, and AXI protocol implementations. You will collaborate closely with system architects, verification engineers, physical design teams, and software/firmware developers to deliver high-performance, power-efficient designs that enable massive-scale AI training and inference.
ASIC Design Engineer - New College Grad 2026 NVIDIA CorpASIC Design Engineer - New College Grad 2026Santa Clara, CAThis position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you'll be doing: As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
High Speed Digital Design Engineer Tesla IncHigh Speed Digital Design EngineerPalo Alto, CA$100,000–$228,000 / yearThe Energy Electrical Engineering team designs the eyes, ears, and brains of Tesla's Vehicle charging & Optimus charging and residential/industrial energy storage products including Powerwall and Megapack. You ll design high-bandwidth data acquisition systems, real-time control processors with multi-gigabit interfaces, signal integrity-critical PCBs, and the digital backbones.