Board Design Engineer Hyve SolutionsBoard Design EngineerFremont, CaliforniaHyve’s integrated ODM, CM, and SI capabilities eliminate vendor complexity while accelerating time-to-market with single-partner accountability from design through scale. As a US-based manufacturing partner, the company rapidly delivers fast, agile execution through dep technical partnerships and co-innovation, and supply chain clarity.
Senior Analog Design Engineer Intel Corp.Senior Analog Design EngineerSanta Clara, CA$141,910–$269,100 / yearMinimum Qualifications: M.S. degree in Electrical Engineering or a related field with 4+ years of industry experience or PhD & 2+ years in the following: Hands-on experience designing high-speed circuit blocks such as amplifiers, drivers, equalizers, PLLs, phase interpolators, and clock and data recovery (CDR) circuits for data rates of 32 Gbps and above. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings.
Senior Manager - Analog Design Advanced Micro Devices IncSenior Manager - Analog DesignSanta Clara, CAThe focus of the activity will be centered around the circuit architecture and design of critical high-speed analog and digital blocks, definition of specifications for the high speed data path; definition of algorithms for calibration, equalization; and development of abstracted models for link performance simulations. Work closely with various disciplines, especially Analog Mixed Signal design, Digital Design and Firmware, as well as Design Verification to ensure optimal implementation of the overall PHY architecture and algorithms and full coverage of the features.
RTL Design & Integration Engineer Advanced Micro Devices, IncRTL Design & Integration EngineerSan Jose, CaliforniaYou will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting PPA, cost and schedule optimized Silicon implementation and first-time-right SW solution. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward.
Rtl2gds IC Sr. Principal Design Engineer CadenceRtl2gds IC Sr. Principal Design EngineerSan Jose, CA$161,000–$299,000 / yearProvide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff. The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology.
SerDes RTL Design Engineer Advanced Micro Devices IncSerDes RTL Design EngineerSan Jose, CATHE ROLE: AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward.
Physical Design CPU Methodology Engineer Tenstorrent IncPhysical Design CPU Methodology EngineerSanta Clara, CAThis role combines deep physical design expertise with organization-level technical leadership, enabling predictable RTL-to-GDS execution, strong PPA outcomes, and scalable methodology adoption across multiple projects and teams. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
Design Verification Engineer - Internal IP EtchedDesign Verification Engineer - Internal IPSan Jose, CaliforniaBacked by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. You will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready.
Design Verification Engineer - Memory Subsystem Qualcomm IncDesign Verification Engineer - Memory SubsystemSanta Clara, CA$153,200–$229,800 / yearThe successful candidate will be responsible for developing and executing comprehensive verification strategies for complex digital designs, including memory controllers, DDR/LPDDR/HBM and custom memory interfaces, PHY-related logic, and other high-performance memory subsystem components. This role involves the complete verification lifecycle-from understanding design specifications and developing verification plans to creating UVM-based testbenches, developing assertions, executing simulations, debugging failures, and driving functional and code coverage closure.
VP of Design OBE Worldwide LLCVP of DesignSan Francisco, CAReporting directly to the Chief Creative Officer, the Vice President, Design leads a multidisciplinary team of designers, including 3D/environmental specialists, graphic and UX/UI designers, and visual storytellers to craft immersive, culturally relevant brand experiences that compete at the level of top design agencies. The Vice President, Design is a senior creative leader responsible for elevating OBE's design excellence, shepherding all design disciplines, and overseeing the development and delivery of world-class experiential, spatial, and integrated design work.
Senior Staff Engineer, GPU Design Verification (Formal Verification) Samsung Electronics America IncSenior Staff Engineer, GPU Design Verification (Formal Verification)San Jose, CA$198,200–$297,200 / yearYou help drive complex debug analysis and root-cause resolution by analyzing formal failures, tracing counterexamples, and collaborating closely with design and architecture teams to ensure verification aligns with architectural intent and improve design robustness. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world.
RFIC Design Engineer , Amazon Leo Amazon.com IncRFIC Design Engineer , Amazon LeoSunnyvale, CAExplore architectures for mm-wave and RF circuits like VCOs, mixers, phase shifters, LNAs, PAs, LO distribution, frequency multipliers and dividers, and envelope/power detectors, and make detailed presentations on power/area/performance trade-offs. Collaborate with communications systems, digital design, and chip implementation teams to specify and implement transceivers and RFIC front-end models which will delight future Kuiper customers.
Hardware Engineer, Accelerator Design Meta Platforms IncHardware Engineer, Accelerator DesignMenlo Park, CAIn this role, you will work across digital design, power delivery, signal integrity, and board-level electrical engineering to bring accelerator systems from concept to production, directly enabling the AI workloads that power Meta's products and services. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.
Physical Design Engineer (Silicon Engineering) Space Exploration TechnologiesPhysical Design Engineer (Silicon Engineering)Palo Alto, CA$135,000–$175,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
ASIC Design Verification Manager, TPU Compute Google LLCASIC Design Verification Manager, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Lead the functional verification team for significant portions of TPU Compute team, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing advanced functional verification infrastructure such as subchip, subsystem, and fullchip level environments.
Sr. Soc/Asic Physical Design Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Soc/Asic Physical Design Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
Sr. Staff Engineer, ASIC Design Ayar Labs IncSr. Staff Engineer, ASIC DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
Principal Design Verification Engineer (Silicon Engineering) SpaceXPrincipal Design Verification Engineer (Silicon Engineering)Sunnyvale, CA$210,000–$310,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
NewRTL Design Engineer, TPU Compute Google LLCRTL Design Engineer, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
RTL Design and Integration Engineer, TPU and ML GoogleRTL Design and Integration Engineer, TPU and MLSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. In this role, you will join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters.