Director of Software Engineering, NX Designer Nextpower IncDirector of Software Engineering, NX DesignerFremont, CA$240,000–$260,000 / yearExpertise in: Backend architecture (Python, Node.js, Java, or similar) Cloud-native databases + caching strategies DevOps, CI/CD, automated QA Scalable compute (containers, serverless, orchestration) API platforms and integration frameworks. At Nextpower, we are driving the global energy transition with an integrated clean energy technology platform that combines intelligent structural, electrical, and digital solutions for utility-scale power plants.
Director Of Software Engineering, NX Designer Nextracker Inc.Director Of Software Engineering, NX DesignerFremont, CA$240,000–$260,000 / yearExpertise in: Backend architecture (Python, Node.js, Java, or similar) Cloud-native databases + caching strategies DevOps, CI/CD, automated QA Scalable compute (containers, serverless, orchestration) API platforms and integration frameworks. At Nextpower, we are driving the global energy transition with an integrated clean energy technology platform that combines intelligent structural, electrical, and digital solutions for utility-scale power plants.
Senior HPC Cluster Engineer NVIDIA CorpSenior HPC Cluster EngineerSanta Clara, CAWe are seeking a highly skilled and experienced HPC Cluster Engineer to design, deploy, and operate GPU Compute Clusters for EDA (Electronic Design Automation) and high-performance computing workloads used across multiple teams and projects. Minimum of 5 years of proven experience crafting and operating large scale compute infrastructure, including cluster configuration managements tools such as BCM or Ansible.
High Speed Analog I/O designer Broadcom IncHigh Speed Analog I/O designerSan Jose, CAJob Description: As a Hardware Engineer, you will play a key role in designing and optimizing cutting-edge interface buffer chips for DDR/LP5/5X/6, chiplets and beyond in the latest FinFET process nodes. Design and enhance transmitter and receiver circuits including CTLE, VGA, DFE and slicers focusing on performance metrics such as sensitivity, linearity and power consumption.
High Speed Analog I/O Designer Broadcom CorporationHigh Speed Analog I/O DesignerSan Jose, CAJob Description: As a Hardware Engineer, you will play a key role in designing and optimizing cutting-edge interface buffer chips for DDR/LP5/5X/6, chiplets and beyond in the latest FinFET process nodes. Design and enhance transmitter and receiver circuits including CTLE, VGA, DFE and slicers focusing on performance metrics such as sensitivity, linearity and power consumption.
Sr. Designer PivotSr. DesignerSan Francisco, CaliforniaWhether planning our Customer Experience program, developing multi-pronged marketing strategies, or designing projects for our innovative clients, we are constantly finding ways to underscore our promise to partner with our clients to make inspiring spaces that unlock their people’s greatest potential. Assume responsibility for the overall completion of projects of all complexities including programming, strategic planning, conceptual designs, space planning, presentations, design development, and production; delegate and oversee fulfillment of design deliverables as required.
Technical Lead, Design Verification Marvell Technology IncTechnical Lead, Design VerificationSanta Clara, CAOur Photonic Fabric delivers a tenfold improvement in performance and energy efficiency deployed as optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB) that integrate into customers'' AI accelerators and GPUs. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Senior System Architect, Hardware Architecture Amazon.com IncSenior System Architect, Hardware ArchitectureSunnyvale, CABesides breadth, you also typically bring depth in one or more areas of expertise to the architecture team, such as computer architecture, SoC architecture, silicon design, graphics and multimedia, embedded Linux, video encoders/decoders, applied machine learning, ML accelerators, audio, wireless, sensors, power management, system performance benchmarking, etc. In the process of architecture definition, you will drive key design decisions such as edge-cloud compute partition, device SoC selection, compute architecture (CPU, DSP, GPU and ML accelerators), and other system component selections (chipsets, memory, storage).
System Architect, Hardware Architecture Amazon.com IncSystem Architect, Hardware ArchitectureSunnyvale, CABesides breadth, you also typically bring depth in one or more areas of expertise to the architecture team, such as computer architecture, SoC architecture, silicon design, graphics and multimedia, embedded Linux, video encoders/decoders, applied machine learning, ML accelerators, audio, wireless, sensors, power management, system performance benchmarking, etc. In the process of architecture definition, you will drive key design decisions such as edge-cloud compute partition, device SoC selection, compute architecture (CPU, DSP, GPU and ML accelerators), and other system component selections (chipsets, memory, storage).
Physical Design Engineering, VP Astera Labs IncPhysical Design Engineering, VPSan Jose, CA$250,600–$375,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Digital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026) Marvell Technology IncDigital Logic + Design Verification Graduate Co-Op Program (US - Fall 2026)Santa Clara, CAThis role is designed for students interested in digital IC design, SoC architecture, and verification methodologies, working on high-performance chips used in the scale up and scale out of AI data centers and other enterprise level applications. To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
Senior Principal Digital Design Engineer Astera LabsSenior Principal Digital Design EngineerSan Jose, CA$205,000–$255,000 / yearThis is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Physical Design Engineering, VP Astera LabsPhysical Design Engineering, VPSan Jose, CA$250,600–$375,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Principal Digital Design Engineer Astera Labs IncSenior Principal Digital Design EngineerSan Jose, CA$205,000–$255,000 / yearThis is a high-impact technical leadership role where youll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. As a senior technical leader, youll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon.
BIM Coordinator / BIM Designer OpenAIBIM Coordinator / BIM DesignerSan Francisco, CAFor unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. You will partner closely with internal engineering teams, external design consultants, contractors, and project stakeholders to produce coordinated BIM deliverables that improve design quality, reduce project risk, and support efficient execution across Industrial Compute's global infrastructure portfolio.
Power Electronics Engineer, AWS Board Core Design Services, Power Team Amazon.com IncPower Electronics Engineer, AWS Board Core Design Services, Power TeamCupertino, CAHardware engineers within AWS Board Core Design & Services team could be working in a variety of areas, few examples would be: hardware design and development; building the systems that validate hardware quality in manufacturing; monitoring and improving hardware reliability in data centers and platform. As a member of the UC organization, you'll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.
Zero Waste Coordinator ABM IndustriesZero Waste CoordinatorSan Francisco, CAFull timeFounded in 1909, ABM provides custom facility solutions in urban, suburban and rural areas to properties of all sizes — from schools and commercial buildings to hospitals, data centers, manufacturing plants and airports. ABM’s comprehensive capabilities include electrical & lighting, energy solutions, facilities engineering, HVAC & mechanical, janitorial, landscape & turf, mission critical solutions and parking, provided through stand-alone or integrated solutions.
Program Manager, MFA in Writing University of San FranciscoProgram Manager, MFA in WritingSan Francisco, CAExperience or background in MFA in Writing areas such as writing, teaching and publishing literature as well as recruitment, admissions and retention in higher education are highly desirable, as is the ability to engage effectively with local literary and cultural organizations and other university arts organizations. Under the general supervision of the Associate Dean for Graduate Programs and Strategic Initiatives, and in coordination with the Program Academic Director, the Program Manager for the MFA in Writing is responsible for managing and supporting the efficient operation of the graduate program.
Kitchen Assistant French Lick ResortKitchen AssistantSan Francisco, CAOur resort includes three hotels (including two AAA Four-Diamond historic hotels), two nationally-acclaimed golf courses, a casino, two world-class spas, over a dozen food and beverage venues, meeting and event facilities, retail shops, horse stables, sporting clays range, bowling alley and more. Soon the Cook family, devoted preservationists who themselves led the restoration of many Indiana buildings, joined the cause and committed more than $600 million dollars to not only save West Baden Springs Hotel but also French Lick Springs Hotel.
Student Intern, Level IV County of Santa ClaraStudent Intern, Level IVSanta Clara, CA$75,855.52–$92,220.96 / yearStudent Eligibility: In order to qualify for the Student Intern classifications, a student must: Have a legal right to work in the United States; Be enrolled in an accredited institution or a school licensed by a state agency or have graduated from such an institution or school within the last six months; Have an overall grade point average of at least 2.5 on a four-point scale; Submit a completed application for employment, unofficial transcript, and proof of enrollment or course schedule for the current school session. To participate in the Student Internship Program, you must provide the following documents: • A copy of your unofficial transcript, official transcript, or a letter from your admissions office that displays your name, school information, declared major, grade point average, and total units/hours accumulated.
Student Intern, Level III County of Santa ClaraStudent Intern, Level IIISanta Clara, CA$62,135.84–$75,541.44 / yearStudent Eligibility: In order to qualify for the Student Intern classifications, a student must: Have a legal right to work in the United States; Be enrolled in an accredited institution or a school licensed by a state agency or have graduated from such an institution or school within the last six months; Have an overall grade point average of at least 2.5 on a four-point scale; Submit a completed application for employment, unofficial transcript, and proof of enrollment or course schedule for the current school session. To participate in the Student Internship Program, you must provide the following documents: • A copy of your unofficial transcript, official transcript, or a letter from your admissions office that displays your name, school information, declared major, grade point average, and total units/hours accumulated.
Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects Google LLCSenior TPU RTL Design Engineer, Networking, Inter-Chip InterconnectsSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Join the team designing and developing the core components of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
Principal Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpPrincipal Design Verification Engineer Silicon EngineeringSunnyvale, CA$210,000–$310,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Silicon Physical Design Engineer Google LLCSilicon Physical Design EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
NewPhysical Design Lead, ASIC Google LLCPhysical Design Lead, ASICSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Implement and execute key design phases: floor-planning, synthesis, placement, clock tree synthesis (CTS), timing closure, routing, extraction, physical verification (design rule checking (DRC)/layout versus schematic (LVS), electromigration (EM)/IR, and final signoff.
NewTPU SoC Design Engineer, Cloud Google LLCTPU SoC Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You will work on top-level RTL, architecture, design and implementation of global communication busses, and integration of complex ASIC designs, as this is a highly cross-functional and central role that will require interactions with numerous ASIC development teams.
Product Marketing III Applied Materials IncProduct Marketing IIISanta Clara, CA$124,000–$171,000 / yearApplied Materials' Semiconductor Products Group (SPG) Strategy & Marketing team is searching for a technical Product Marketer with a deep interest in semiconductor manufacturing technologies and a rare ability to bridge rigorous technical content with compelling creative storytelling. This role sits at the intersection of process engineering, product strategy, and narrative-driven marketing, translating complex semiconductor process technologies into clear, differentiated, and visually engaging stories for both technical and executive audiences.
Student Intern, Level II County of Santa ClaraStudent Intern, Level IISanta Clara, CA$52,093.60–$63,333.92 / yearStudent Eligibility: In order to qualify for the Student Intern classifications, a student must: Have a legal right to work in the United States; Be enrolled in an accredited institution or a school licensed by a state agency or have graduated from such an institution or school within the last six months; Have an overall grade point average of at least 2.5 on a four-point scale; Submit a completed application for employment, unofficial transcript, and proof of enrollment or course schedule for the current school session. To participate in the Student Internship Program, you must provide the following documents: • A copy of your unofficial transcript, official transcript, or a letter from your admissions office that displays your name, school information, declared major, grade point average, and total units/hours accumulated.
Digital Marketing Specialist ASUSTeK Computer IncDigital Marketing SpecialistFremont, CA$75,000–$95,000 / yearThis position is responsible for executing and optimizing paid media campaigns, managing ASUS owned digital properties (excluding social platforms), supporting SEO initiatives, and leading the ASUS U.S. affiliate marketing program. This role collaborates closely with cross-functional teams including product, sales, ecommerce, channel, accounting, and creative teams to support product launches, promotions, and integrated marketing initiatives.
New["Managing Consultant, Landscape Architecture","Managing Consultant, Landscape Architecture"] Erm LLC["Managing Consultant, Landscape Architecture","Managing Consultant, Landscape Architecture"]San FranciscoRemote$79,395–$101,693 / yearAs new energy infrastructure, high-tech manufacturing and employment, and brownfield redevelopment projects emerge to meet growing demand for reliability and resilience, thoughtful integration of infrastructure projects into the existing landscape are essential. Driver's License Required: This position requires a valid driver's license and/or the ability to operate a company vehicle due to the nature of job duties, which may include occasional travel to various client locations across a large geographical area.
Content Specialist, Customer Education HarveyContent Specialist, Customer EducationSan Francisco, California$94,000–$126,000 / yearSitting within the Customer Education team and reporting to the Head of User Operations, you’ll focus on creating and optimizing Help Center content that empowers customers to self-serve effectively and understand our products with clarity and confidence. Regularly review customer questions, search behavior, and feedback to identify unclear or missing content, and update articles proactively to improve the usefulness of self-service resources.
Senior Manager, IT SOX Compliance NvidiaSenior Manager, IT SOX ComplianceSanta Clara, CAWe are well positioned as the 'AI Computing Company', and our GPUs are the brains powering Deep Learning software frameworks, accelerated analytics, big data, modern data centers, and driving autonomous vehicles. What you'll be doing: Lead the lifecycle of IT SOX compliance, including risk assessment, scoping, control design, and testing to mitigate technology and data risks tied to financial reporting.
Corporate Communications Specialist LendingClubCorporate Communications SpecialistSan Francisco, California$70,000–$82,000 / yearThis role is ideal for someone eager to grow their career in communications, explore the evolving role of AI in corporate storytelling, and make an immediate impact on how employees and media engage with our company. Join our Corporate Communications team as a Corporate Communications Specialist, where you’ll help bring the Happen Bank brand to life with internal and external audiences.
Senior Software Engineer - Fleet LambdaSenior Software Engineer - FleetSan Francisco, CaliforniaOur investors notably include TWG Global, US Innovative Technology Fund (USIT), Andra Capital, SGW, Andrej Karpathy, ARK Invest, Fincadia Advisors, G Squared, In-Q-Tel (IQT), KHK & Partners, NVIDIA, Pegatron, Supermicro, Wistron, Wiwynn, Gradient Ventures, Mercato Partners, SVB, 1517, and Crescent Cove. Exposure to DPU-adjacent networking, storage, or security technologies such as OVS/OVN, BGP/FRR, SR-IOV/VFs, DOCA, NVMe emulation , telemetry agents, or certificate-based service authentication.
Project Manager Skidmore Owings & MerrillProject ManagerSan Francisco, CaliforniaDemonstrates an advanced understanding of planning and urban design concepts, building typologies, critical dimensions and systems, utility and infrastructure systems, land development imperatives and planning / zoning codes, and phasing and implementation techniques. Manages time and workload of own work efforts and those of others to meet project task deadlines and commitments, with occasional interaction and direction from team leaders while guiding and teaching less experienced staff.
Senior Technical Architect - Mandarin Speaking Skidmore Owings & MerrillSenior Technical Architect - Mandarin SpeakingSan Francisco, CaliforniaInspires and leads others by example, participates in staff mentoring and training, clearly defines team member expectations and responsibilities, empowers others, and delegates where appropriate based on team members’ recognized abilities and potential. Creates and innovates with a strong conceptual design ability and integrates interdisciplinary criteria to effectively move forward the design of distinct portions of large projects or entire projects of a small scale.
Senior BIM Specialist - Structural Skidmore Owings & MerrillSenior BIM Specialist - StructuralSan Francisco, CaliforniaDemonstrated ability to create and coordinate complex BIM / Revit structural building models and assemble drawing deliverable packages at all levels of detail and project stages. Creates, develops, and manages the BIM model and drawings for structural engineering components of projects.
BIM Lead Skidmore Owings & MerrillBIM LeadSan Francisco, CaliforniaLeads definition, planning and documentation of digital work-flow strategies, objectives and coordination of data management on Projects through close collaboration with Project Digital Coordinators as well as fellow leaders in Computational Design, High Performance Design, Visualization, etc. Minimum 8 years of focused professional experience in applying and developing digital tools and processes to AEC project work, including experience in Revit to document a variety of large-scale building projects.
Project Manager- Interiors Skidmore Owings & MerrillProject Manager- InteriorsSan Francisco, CaliforniaInspires and leads others by example, participates in staff mentoring and training, clearly defines team member expectations and responsibilities, empowers others, and delegates where appropriate based on team members’ recognized abilities and potential. Effectively communicates internally with project teams and externally with consultants and clients through timely and appropriate written, oral, and visual means.
Smts Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O) Micron Technology, Inc.Smts Analog Design Engineer, Mixed-Signal PHY (Clocking & High-Speed I/O)San Jose, CA$159,000–$347,000 / yearKey design domains include clocking architecture (PLL/DLL, clock distribution, jitter budgeting, clock recovery), transmitter design (high-speed output drivers, pre-emphasis, swing/impedance control), receiver design (sense amplifiers, CTLE/DFE equalization, samplers), bias and reference generation, and calibration architecture. As a Principal Analog Design Engineer, you will be a core technical contributor on a small, senior team spanning analog design, layout, silicon characterization, digital design, and physical design - united around the goal of preparing high-speed interface innovations for high-confidence product adoption.
Growth Designer & Video Editor (Contract) 23andMe IncGrowth Designer & Video Editor (Contract)Palo Alto, CAEnd-to-End Asset Production: Design and edit high-volume static, motion, and video assets for Paid Media and owned & operated channels such as our e-commerce website, Email, Google, YouTube, Facebook, Instagram, Reddit, Amazon, TikTok, and Influencers, among others. Platform-Native Storytelling: Develop content that feels native to each environment, from lo-fi, high-trust UGC-style edits for TikTok to high-authority, polished motion graphics for YouTube and LinkedIn.
Brand Designer Pump.coBrand DesignerSan Francisco, California$110,000–$180,000 / yearCollaborate cross-functionally on brand evolution, content strategy, and integrated marketing campaigns, partnering closely with marketing teams to drive audience engagement and demand generation. This is a high-impact, creative-first role where you’ll collaborate across marketing, product, and leadership teams to define how the world sees and experiences Pump.
Visual Communication Designer for Internal Communications Apple IncVisual Communication Designer for Internal CommunicationsCupertino, CACreative and innovative thinker with a portfolio that demonstrates advanced expertise in creative presentation design (especially Keynote), web design, UI/UX design, and other visual communication materials that showcase an aesthetic aligned with Apple's visual identity.5+ years of design experience, with a proven track record in developing compelling Keynote presentations and visual communication assets specifically for internal audiences. Manage projects from ideation through to execution, coordinating with cross-functional teams to ensure timely delivery of high-quality designs.3 years of design experience in a dynamic, fast-paced environment, demonstrating an ability to manage high volumes of work without sacrificing quality.
NewEngineering Associate I (Engineering Drafter) - Project Design & Development - Public Works (5364) City and County of San FranciscoEngineering Associate I (Engineering Drafter) - Project Design & Development - Public Works (5364)San Francisco, CAThe staff designs and manages the construction of civic buildings and streets; cleans and greens the right of way; maintains civic buildings; manages multi-million-dollar bond programs; trains people for jobs; keeps the right of way free of hazards; paves the roads; repairs bridges and public stairways; expands accessibility; and works at the forefront addressing some of San Francisco's biggest challenges. MINIMUM QUALIFICATIONSExperience: Four (4) years of verified civil (including structural /or transportation) technical engineering drafting experience using CAD or BIM systems to prepare engineering drawings and other engineering graphic material, at least two (2) years of which must have been in a position with duties comparable to those of Class 5362 Engineering Assistant.
BAS Design Engineer ControlsJobsBAS Design EngineerSan Jose, CaliforniaAbout the Opportunity: A long-standing, stable Building Automation contractor is seeking a skilled BAS Design Engineer to join their engineering team in San Jose, CA. This role is ideal for mid-level to senior-level professionals with strong design capabilities in HVAC and Building Automation Systems.
Technical Lead, IC Design MarvellTechnical Lead, IC DesignSanta Clara, CAExperience in micro-architecture of complex custom/ASIC products, focusing in one or more of the following areas: NPU, embedded processors, DSP, graphics, and general-purpose microprocessors. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Design Engineer, Brand InfisicalDesign Engineer, BrandSan Francisco, CaliforniaYou’ll work closely with our co-founder and the Marketing, Sales, and Developer Experience teams to: Define and evolve Infisical’s brand identity, including the visual language, creative direction, and level of craft across everything we put into the world. Strong design and engineering skills, with experience building polished digital experiences and a portfolio demonstrating exceptional visual craft, creativity, and technical execution.
BIM Coordinator / BIM Designer OpenAI LLCBIM Coordinator / BIM DesignerSan Francisco, CAFor unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. You will partner closely with internal engineering teams, external design consultants, contractors, and project stakeholders to produce coordinated BIM deliverables that improve design quality, reduce project risk, and support efficient execution across Industrial Computes global infrastructure portfolio.
Senior GPU Architect NVIDIA CorpSenior GPU ArchitectSanta Clara, CAWe are constantly looking for ways to improve our GPU architecture and maintain our leadership by developing new parallel programming models, new architectures and new infrastructure that is required to make this successful. In this position, you will be responsible for developing and enhancing various features in the GPU architecture that advance the state of the art in graphics features, graphics performance, parallel programming models or parallel computing performance.
Applied Research Engineer, Chip Design NVIDIA CorpApplied Research Engineer, Chip DesignSanta Clara, CALarge language models, coding agents, and agentic AI are transforming how chips get designed, and this role puts you at the frontier - applying the latest and greatest AI to NVIDIA's real ASIC design flows and pushing past the limits of what's currently possible. Domain and technical expertise in front-end ASIC (design, verification, timing) combined with project experience applying agentic AI to chip design and optimization problems, with a track record of driving ideas from conception through experimentation to production.