Harness Design Engineer Astro Digital US IncHarness Design EngineerSan Jose, CAAstro Digital designs, builds, and operates a diverse range of small satellite systems supporting space-based turnkey missions for several business applications, including earth observation, communications, in-orbit demonstrations, risk reduction, science, and exploration. Youll work at the intersection of electrical design, systems integration, and hands-on hardware, collaborating closely with the different engineering teams to deliver flight-ready wiring harnesses that perform flawlessly in the harshest environments imaginable.
Principal RFIC/PLL Design Engineer Blue Origin Enterprises LPPrincipal RFIC/PLL Design EngineerCA$230,773–$323,081.85 / yearand/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
Director of Design (UI/UX + Brand) GantriDirector of Design (UI/UX + Brand)San Francisco, CAWe’re looking for a Director of Design to lead brand design, UI/UX, and creative at Gantri — someone with exceptional taste and a track record of building cohesive, elevated brand experiences for design-forward, tech-enabled consumer companies. Lead the UI/UX vision for gantri.com , MadeOS (our custom manufacturing platform) and our industry-leading FactoryOS software, ensuring the digital experience reflects the quality and intentionality of our brand.
NVIDIA 2027 Internships: Hardware Design for Test (DFT) NVIDIA CorpNVIDIA 2027 Internships: Hardware Design for Test (DFT)Santa Clara, CACourse or internship experience related to the following areas could be required: Design for Test (DFT), Digital Design, Test Architecture and DFT Planning, Static Timing Analysis (STA), Pre-Silicon and Post-Silicon Issue Debug. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society - from gaming to robotics, self-driving cars to life-saving healthcare, climate change to virtual worlds where we can all connect and create.
Sr. RTL Design Engineer RivianSr. RTL Design EngineerPalo Alto, CaliforniaFull timeRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services.
VP of Design OBE Worldwide LLCVP of DesignSan Francisco, CAReporting directly to the Chief Creative Officer, the Vice President, Design leads a multidisciplinary team of designers, including 3D/environmental specialists, graphic and UX/UI designers, and visual storytellers to craft immersive, culturally relevant brand experiences that compete at the level of top design agencies. The Vice President, Design is a senior creative leader responsible for elevating OBE's design excellence, shepherding all design disciplines, and overseeing the development and delivery of world-class experiential, spatial, and integrated design work.
Digital IC Design Engineer Intern NeuralinkDigital IC Design Engineer InternSouth San Francisco, CAJob Description and Responsibilities: We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces.
Design Verification Engineer (Silicon Engineering) SpaceXDesign Verification Engineer (Silicon Engineering)Palo Alto, CA$135,000–$155,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Sr. ASIC Design Verification Engineer (Silicon Engineering) SpaceXSr. ASIC Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
ASIC Design Verification Engineer, TPU GoogleASIC Design Verification Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
TPU RTL Design Engineer GoogleTPU RTL Design EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Design Verification Engineer, Silicon GoogleDesign Verification Engineer, SiliconMountain View, CADevelop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Plan the verification of complex digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios.
Silicon Design Verification Engineer GoogleSilicon Design Verification EngineerMountain View, CADevelop and enhance constrained-random verification environments using SystemVerilog and universal verification methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA). Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
TPU SoC Design Engineer, Cloud GoogleTPU SoC Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
RTL Design and Integration Engineer, TPU and ML GoogleRTL Design and Integration Engineer, TPU and MLSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. In this role, you will join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters.
Board Design Engineer TaaraBoard Design EngineerSunnyvale, CaliforniaThe position seeks highly-motivated individuals that enjoy working in a small dynamic team environment, with a passion for solving challenging problems that can lead to high-impact advances in technology. They’ll work closely across teams including photonics integrated circuits, electronic integrated circuit, mechanical design and software in developing the board designs.
Physical Design Engineer (Silicon Engineering) SpaceXPhysical Design Engineer (Silicon Engineering)Palo Alto, CA$135,000–$175,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Sr. Asic Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Asic Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.
Startup Design Accelerator (Remote) UX WomanStartup Design Accelerator (Remote)San Francisco, CARemoteTell a compelling story about users by showcasing user types, personas, stakeholder maps, journey maps, process maps, service blueprints, ideation matrixes, sketches, wireframes, UX workflows, prototypes and other visual deliverables. Lead discovery research by managing user recruitment, creating research plans, writing interview guides, leading 8-16 discovery interviews, and synthesizing interview insights.
Physical Design Engineer (Silicon Engineering) Space Exploration TechnologiesPhysical Design Engineer (Silicon Engineering)Palo Alto, CA$135,000–$175,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.