Senior Principal RF Digital Design Integration & Test Engineer RTXSenior Principal RF Digital Design Integration & Test EngineerTexasThis department is responsible for full-scope Independent Design, Verification & Validation (IV&V) solutions for antenna products, including architecture trades, design, development, integration, deployment, and sustainment of antenna systems and associated integrated system verification solutions. Typically requires a Bachelor’s in Science, Technology, Engineering, or Mathematics (STEM) and a minimum of 10 years of prior relevant experience to include any combination of the following: Experience in RF passive circuit design and EM modeling.
NewPrincipal, EMC/EMI Design Engineer (Onsite) RTXPrincipal, EMC/EMI Design Engineer (Onsite)Richardson, TexasEfforts are typically to support nuclear radiation characterization testing of circuit card assemblies (CCA) for radio and display systems to ensure compliance in specialized environments such as Total Ionizing Dose, Neutron Displacement Damage, Ionizing Dose Rate, and Single Event Effects. In this EMC/EMI Electrical Engineer role, you will support the following types of activities: Collaborate with a multi-discipline team of Engineers to develop reliable, high‑performance hardware designs that meet system requirements and operational specifications.
Senior ASIC/FPGA Design Engineer RTXSenior ASIC/FPGA Design EngineerTexasThe selected candidate will define ASIC/FPGA requirements from system specifications, develop digital architectures, implement RTL designs, and perform timing, power, and functional analysis. As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.
Digital Design Coordinator HDR, Inc.Digital Design CoordinatorSan Antonio, TXOur eight Employee Network Groups (Asian Pacific, Black, Hispanic/Latino(a), LGBTQ, People with Disabilities, Veterans, Women, Young Professionals) help create a sense of belonging and foster a supportive environment where everyone is empowered to engage and contribute. At HDR, our employee-owners are fully engaged in creating a welcoming environment where each of us is valued and respected, a place where everyone is empowered to bring their authentic selves and novel ideas to work every day.
Senior Silicon Physical Design Engineer - TeraWave Blue OriginSenior Silicon Physical Design Engineer - TeraWaveSan Diego, Texasand/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
Staff Electrical Design Engineer Fab2Staff Electrical Design EngineerAustin, TexasYou will know you are successful when you have autonomously taken clean-sheet designs through to production, delivering reliable, tested electrical systems that our in-house production team can seamlessly assemble into our fab tools. Own the clean-sheet design of PCBAs and electrical systems for our machines, driving the end-to-end process including schematic capture, layout, bringup, testing, integration, and documentation.
Principal Digital Hardware Design Engineer -Onsite RTXPrincipal Digital Hardware Design Engineer -OnsiteTexasExpertise with Xpedition's Constraint Editor System (CES), routing practices for high-speed signals, and guiding Electronic Computer-Aided Design (ECAD) personnel through PCB layout and technical drawing creation. As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote.
Senior Digital Hardware Design Engineer - Onsite RTXSenior Digital Hardware Design Engineer - OnsiteTexasAs part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote. Experience with Xpedition's Constraint Editor System (CES) and guiding Electronic Computer-Aided Design (ECAD) personnel through PCB layout and technical drawing creation.
Digital Design Specialist: Structural Engineering LPADigital Design Specialist: Structural EngineeringDallas, TexasLPA’s structural engineers have been repeatedly recognized by our peers in the structural engineering community for our innovative and technically challenging designs, including receiving SEAOC’s Excellence in Structural Engineering and People’s Choice Award in 2021 along with multiple national engineering awards from NCSEA and AISC. Opportunities to propose and lead projects that impact your local community, including more than $1 million since 2015 in Habitat for Humanity builds, scholarships, and other pro bono community projects.
Senior Physical Design Methodology Engineer, PPA Fusion Compiler NvidiaSenior Physical Design Methodology Engineer, PPA Fusion CompilerAustin, TXNVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer, PPA Fusion Compiler to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis and back-end verification across multiple projects along with chip floorplan, power and clock distribution, chip assembly.
Senior ASIC Design Engineer – Clocks IP NVIDIASenior ASIC Design Engineer – Clocks IPAustin, CaliforniaImprove Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Senior Asic Design Engineer - Clocks IP NvidiaSenior Asic Design Engineer - Clocks IPAustin, TXImprove Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Senior ASIC Floorplan Design Engineer NVIDIASenior ASIC Floorplan Design EngineerAustin, CaliforniaThis position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
Senior Physical Design Engineer NVIDIASenior Physical Design EngineerAustin, CaliforniaAlready a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics. As a member of a team, we will all participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
Senior Physical Design and Timing Engineer NVIDIASenior Physical Design and Timing EngineerAustin, CaliforniaStrong hands-on experience taking complex blocks, IPs, or chips from RTL/netlist to tapeout through logic synthesis, floorplanning, placement, clock-tree synthesis, routing, physical optimization, signoff, and ECOs. Hands-on experience in block, sub-chip, and full-chip level Static Timing Analysis, timing-constraint development, and multi-mode, multi-corner timing closure factoring in process variations, IR drop, and Xtalk.
NewSenior Asic Floorplan Design Engineer NvidiaSenior Asic Floorplan Design EngineerAustin, TXThis position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you will be doing: Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
NewSenior Physical Design And Timing Engineer NvidiaSenior Physical Design And Timing EngineerAustin, TXStrong hands-on experience taking complex blocks, IPs, or chips from RTL/netlist to tapeout through logic synthesis, floorplanning, placement, clock-tree synthesis, routing, physical optimization, signoff, and ECOs. Hands-on experience in block, sub-chip, and full-chip level Static Timing Analysis, timing-constraint development, and multi-mode, multi-corner timing closure factoring in process variations, IR drop, and Xtalk.
Principal Silicon Design Verification Engineer Microsoft CorpPrincipal Silicon Design Verification EngineerAustin, TX$142,800–$274,800 / yearRequired Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. 10+ years of experience in pre-silicon validation with a proven track record of delivering high performance Network switches/accelerators, Central Processing Unit (CPU), Vector processors and Graphics Processing Unit (GPU's) or relevant experience.
Senior Digital Design Engineer NVIDIASenior Digital Design EngineerAustin, CaliforniaAs a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks. We have some of the most forward-thinking and hardworking people in the world working for us, and, due to outstanding growth, our special engineering teams are growing fast.
Asic Physical Design Engineer, Netlisting - New College Grad 2026 NvidiaAsic Physical Design Engineer, Netlisting - New College Grad 2026Austin, TXWhat you'll be doing: Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.