Working closely with our architects and the silicon, hardware, networking, and software teams, you''ll capture workload behavior, extend simulation and analytical models of our silicon, interconnect, and multi-hop fabrics, and validate them against real hardware. Model how serving strategies (tensor, pipeline, and expert parallelism, prefill/decode disaggregation, batching, and KV-cache placement) interact with Tensordyne silicon and fabric topology, and measure the effect on latency, throughput, and cost per token.