Transistor-level design, simulation, and verification of high-performance SerDes circuits, including advanced receiver equalizers (CTLE/FFE/DFE), CDR loops, high-speed current-mode drivers, pre-emphasis/de-emphasis stages, termination networks, clock-generation circuits (VCOs, PLLs, phase interpolators, clock dividers), L/C tank oscillators, charge pumps, bandgap/bias circuits, and clock management units. Requirements: Must have a Master's degree in Electronic Engineering, Electrical Engineering, or closely related technical discipline (willing to accept foreign education equivalent) and five (5) years of experience in the proffered role or related occupation performing analog and mixed-signal IC design in engineering or a related role focused on analog and mixed-signal IC design.