Senior Physical Design Engineer Samsung SemiconductorSenior Physical Design EngineerSan Jose, CA$138,000–$206,000 / yearTo achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future.
Staff Systems Integration Engineer ALSOStaff Systems Integration EngineerPalo Alto, California$190,000–$220,000 / yearWe’re a passionate team of builders, dreamers, doers and innovators, focused on creating entirely new (not to mention, innovative and delightful) vertically integrated, small EVs designed to meet the global mobility challenges of today and tomorrow. Oversee the design, implementation, and management of automated test processes, focusing on efficiency and scalability, and help build a test asset strategy to ensure the availability, deployment, and performance of testing resources.
Data Center Infrastructure Engineer (Contract) Caltek StaffingData Center Infrastructure Engineer (Contract)San Jose, CA$70–$100 / hourThis individual will serve as the owner's technical representative for critical server room infrastructure projects, ensuring electrical, HVAC, and facility systems are properly designed, upgraded, and capable of supporting current and future hardware deployments. Bachelor's degree in Electrical Engineering, Mechanical Engineering, Facilities Engineering, or related technical discipline (or equivalent experience).
Radio Frequency Engineer Oleo Sustainable Palm Oil SolutionsRadio Frequency EngineerBerkeley, CaliforniaYour core responsibility will be developing the design principles and RF architecture required to achieve uniform, homogeneous heating throughout a custom microwave applicator operating at industrial scale, including optimal geometry. Oleo is supported by Activate, DOE Leep @ Cyclotron Road, and BEAM Circular, and has received investment from Gener8tor, Safar Partners, Alpine Social Ventures, Collab Fund, and G-Force.
Sr. Physical Design Engineer LumilensSr. Physical Design EngineerSan Jose, CaliforniaIn this role, you will own physical implementation from RTL to GDSII, drive timing and power closure for ultra-high-speed designs, and work closely with RTL, STA, IP, and verification teams to solve complex implementation challenges unique to advanced-node and high-speed transceiver architectures. Advanced Physical Design: Apply physical design techniques for multi-voltage and multi-frequency domains, hierarchical implementation, physical-aware synthesis, congestion mitigation, skew optimization, and RC extraction-aware placement and routing.
Senior/Principal Analog & Mixed Signal Design Engineers LumilensSenior/Principal Analog & Mixed Signal Design EngineersSan Jose, CaliforniaWe are seeking an experienced Analog / Mixed-Signal IC Design Engineer to design and deliver high-performance Driver and TIA circuits in BiCMOS and advanced semiconductor nodes. This role involves end-to-end ownership of analog building blocks, from architectural definition through silicon validation, in a fast-moving and technically rigorous environment.
IC/RTL Design Engineer LumilensIC/RTL Design EngineerSan Jose, CaliforniaPower- and timing-aware design — managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks. You design and implement the digital front-end RTL at the heart of the chip — including the high-speed datapath that moves data between UCIe and the optical front end.
Lead RTL Design Engineer Cerebras SystemsLead RTL Design EngineerSunnyvale, California$175,000–$275,000 / yearYou will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.
Design Engineer ReplitDesign EngineerFoster City, CAIn this role, you'll help shape our design system implementation, architect front-end solutions, and ensure seamless user experiences across our platform. With millions of users worldwide, Replit is democratizing software development by removing traditional barriers to application creation.
Physical Design Engineer - Block Level, Subsystem Implementation Etched AIPhysical Design Engineer - Block Level, Subsystem ImplementationSan Jose, CAYou will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market. Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis.
Senior Analog IC Design Engineer Lattice Semiconductor CorporationSenior Analog IC Design EngineerSan Jose, CAProven design experience in most of the following analog, mixed-signal circuits: SerDes receivers/transmitters, low-jitter PLLs, oscillators, phase interpolators, ADC/DAC, high speed clock distribution, bandgap/bias, and voltage regulators. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry.
Physical Design Engineer Etched AIPhysical Design EngineerSan Jose, CAwill own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed. Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis.
NewDesign Engineer GumloopDesign EngineerSan Francisco, CaliforniaYou’ll own key user-facing surfaces from early concept through final implementation, using strong product judgment, thoughtful interaction design, and excellent frontend execution to make complex workflows feel simple. You’ll also help evolve our design system and establish reusable patterns that make the product better over time, and allow the rest of our engineering team to build beautiful interfaces.
Senior Principal Analog Design Engineer QorvoSenior Principal Analog Design EngineerSan Jose, CA$193,100–$251,100 / yearIn this role, you will drive architecture, design, and validation of industry-leading analog power ICs, collaborating closely with cross-functional global teams to deliver world-class products that set new benchmarks in efficiency, reliability, and performance. Qorvo's fast-growing Power Management division is at the forefront of innovation in Power Loss Protection, PMICs, Motor Control, and Battery Management solutions, serving a diverse range of applications across Mobile, Consumer, IoT, and Industrial markets.
MTS - Design Engineer Ironsite AIMTS - Design EngineerSan Francisco, CaliforniaIronsite is backed by leading investors (8VC, South Park Commons, Saga Ventures) and prominent operators across technology and construction, including Eric Schmidt, Jeff Dean, Jeff Rothschild, Mark Leslie, Scott Wu, Eric Glyman, Karim Atiyeh, Russell Kaplan, and others, alongside over a dozen construction industry operators who have joined us as partners in building this. We are accelerating the speed, efficiency, and predictability of construction, especially for complex, mission-critical infrastructure projects, including data centers, LNG facilities, sports stadiums, hospitals, and other large-scale developments, by training AI models on egocentric construction footage and labor productivity data.
NewSenior Module Design Engineer QorvoSenior Module Design EngineerSan Jose, CA$115,600–$150,500 / yearQorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Module level design from concept to production, including integration of PAs, LNAs, filters, and switches into highly compact multilayer modules.
NewSenior Electrical Power Design Engineer, LV Electronics General MotorsSenior Electrical Power Design Engineer, LV ElectronicsSunnyvale, CA$106,600–$163,400 / yearIn-vehicle electronics is a fast-growing technology in the global automotive industry featuring many cutting-edge technologies such as Compute, body and zone controllers, multi-view cameras, Gig+Ethernet, PCIe, digital/analog interfaces and more. Build, test, and validate power delivery systems on prototypes, using lab equipment like oscilloscopes, power analyzers, and thermal cameras to ensure they meet design specifications.
NewPrincipal ASIC Design Engineer Hewlett Packard EnterprisePrincipal ASIC Design EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
NewPrincipal Physical Design Engineer Hewlett Packard EnterprisePrincipal Physical Design EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
ASIC/RTL Design Engineer Saicon Consultants IncASIC/RTL Design EngineerSAN JOSE, CAOur RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams. EXPERIENCE AND EDUCATION: SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.