NewFEA Packaging Engineer CspeedFEA Packaging EngineerPalo Alto, CaliforniaOur executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware. Expert proficiency in one commercial FEA or CFD tool and working proficiency in a second covering the other domain — for example Ansys Mechanical or Abaqus alongside Icepak, Fluent, Flotherm, or Celsius.
Senior Si Photonics Design Engineer MolexSenior Si Photonics Design EngineerFremont, CAFull timeReporting to the Manager of Si Photonics (SiPho) Component Design, you will be a key member of the team and will contribute to various aspects of PIC development including design and optimization of passive and active SiPho components, EVT/DVT of optical devices and circuits, and collaboration with the layout, test, reliability, signal integrity, and integration teams. The Senior Si Photonics Design Engineer will provide design support for existing and advanced photonic technology and collaborate with global, cross-functional teams and supplier partners to develop next-generation photonic solutions.
Lidar Test & Calibration Engineer Aeva Technologies Inc.Lidar Test & Calibration EngineerMountain View, CA$103,900–$140,600 / yearWhat you'll have: 1-3 years of experience (or equivalent academic project experience) developing test processes and infrastructure for optoelectronic products such as LiDAR, laser-based sensors, optical systems, cameras, or imaging systems. Role Overview: We are seeking a highly motivated LiDAR Test & Calibration Engineer to develop, optimize, and support manufacturing test and calibration processes for LiDAR sensors in a high-volume production environment.
Sr. Staff Engineer, ASIC Design Ayar Labs IncSr. Staff Engineer, ASIC DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
Engineer, Product and Test Hardware Design Ayar Labs IncEngineer, Product and Test Hardware DesignSan Jose, CA$130,000–$160,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Using schematics, drawings, and direct interaction with our Design and Product teams, this person will develop and bring up the probe cards and circuitry we use to test our next-generation TeraPHY and SuperNova devices.
Camera Hardware Engineer, Robot Head 1XCamera Hardware Engineer, Robot HeadSan Carlos, CaliforniaThey are equally comfortable designing rigorous validation methods, analyzing image quality, debugging hardware in the lab, and partnering with cross-functional teams to deliver production-ready vision systems that enable reliable robotic perception. Working closely with Computer Vision, Machine Learning, Electrical Engineering, Mechanical Engineering, and Manufacturing teams, you'll help deliver robust camera systems that perform reliably across millions of operating hours in real-world environments.
Senior Opto Mechanical Design Engineer Aeva Technologies Inc.Senior Opto Mechanical Design EngineerMountain View, CA$154,900–$209,600 / yearWithin the range, the successful candidate's starting base pay will be determined based on factors including job-related skills, experience, certifications, qualifications, relevant education or training, and market conditions. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.
Sr. Staff Engineer, Analog/Mixed-Signal Design Ayar Labs IncSr. Staff Engineer, Analog/Mixed-Signal DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. As an Analog and Mixed Signal Design Engineer, you will design various blocks such as oscillators, high speed transmitters/receivers, biasing circuits, linear regulators, ADCs/DACs, and others.
Principal, System Reliability Engineer Ayar Labs IncPrincipal, System Reliability EngineerSan Jose, CA$185,000–$290,000 / yearThis role owns reliability qualification at the system and fleet level: building the test infrastructure and evidence base that proves our products are ready for large-scale deployment, and then partnering directly with customers and integration partners to carry that evidence through joint qualification programs and pilot deployments. Fault injection and lifecycle monitoring: Design and run fault-injection and failure-mode testing, including scenarios that exercise field-serviceable components under representative operating conditions, in partnership with customer and integration-partner operations teams.
Engineer, Test Software Ayar Labs IncEngineer, Test SoftwareSan Jose, CA$130,000–$160,000 / yearBacked by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Required Qualifications: BS in Electrical Engineering, Computer Science, or related field with 1+ years of industry experience; or MS in Electrical Engineering, Computer Science, or related field with 0-2 years of industry experience.
Senior, Electrical Engineer Tokyo Electron LtdSenior, Electrical EngineerFremont, CA$158,825.94–$224,411.07 / yearExpertise in at least one relevant area, such as low-noise analog, mixed-signal electronics, embedded controls, precision instrumentation, industrial controls, motion, thermal control, or power systems. The work spans low-noise and mixed-signal electronics, industrial controls, power, motion and thermal control, optical instrumentation, safety circuits, and sensors.
Principal Engineer, SerDes AMS Design and Architecture Ayar Labs IncPrincipal Engineer, SerDes AMS Design and ArchitectureSan Jose, CA$200,000–$260,000 / yearBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Key Responsibilities: Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
DFM PCBA Engineer Apple IncDFM PCBA EngineerCupertino, CAOpportunities to Grow and Develop: This role provides an unparalleled opportunity to deepen your expertise in: Holistic PCBA and process design optimization, balancing competing considerations such as assembly material selection and validation, cutting-edge process development, reliability, environmental footprint reduction, raw material usage, cost, quality, and factory throughput. Your expertise will be critical in developing, productizing, and mass producing some of the world's most challenging consumer PCBA designs, ensuring unparalleled quality, reliability, and cost-effectiveness from concept through high-volume manufacturing, all while minimizing our environmental footprint.
Lead Systems/Dsp Engineer EthernoviaLead Systems/Dsp EngineerSan Jose, CA$180,000–$250,000 / yearJoin Ethernovia's team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. We are well-funded and backed by some of the worlds' leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date: Ethernovia Raises Over $90 Million Series B to Scale Leading-Edge Autonomy and Physical AI Networking Chips.
NewLead Systems/DSP Engineer EthernoviaLead Systems/DSP EngineerSan Jose, California$180,000–$250,000 / yearJoin Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. We are well-funded and backed by some of the worlds’ leading technology investors, having secured $154M ($90+M Series-B and $64M Series-A) in total funding to date: Ethernovia Raises Over $90 Million Series B to Scale Leading-Edge Autonomy and Physical AI Networking Chips .
New Product Manufacturing Engineer CACI International Inc.New Product Manufacturing EngineerLos Gatos, CA$86,600–$181,800 / yearCross-Functional Collaboration: Report to the program manager and interact with other small program teams to coordinate activities across build, unit test, design engineering, supply chain, material handling, and quality assurance. Pay Range: There are a host of factors that can influence final salary including, but not limited to, geographic location, Federal Government contract labor categories and contract wage rates, relevant prior work experience, specific skills and competencies, education, and certifications.
Sr. Principal Photonics engineer II-VI Optical Systems, Inc.Sr. Principal Photonics engineerSanta Clara, CAEnergy-efficient optical I/O: develop architecture options for high-density, short-reach optical links relevant to memory-adjacent, scale-up, and disaggregated-compute use cases; compare parallel-emitter arrays, silicon photonics, and emerging emitter / receiver concepts using link-level and packaging-level metrics. Advanced light sources for silicon photonics: evaluate source architectures such as quantum-dot DFB lasers, PIC-enhanced approaches, and comb-based sources against power, wavelength control, integration, reliability, packaging, manufacturability, and platform fit.
NewSenior Photonic Circuits Design Engineer Taara Connect IncSenior Photonic Circuits Design EngineerSunnyvale, CATaara is seeking a Senior Photonic Circuits Design Engineer to work on next-generation photonic and electronic integrated modules as part of the R&D team developing cutting-edge wireless optical communication systems based on integrated optical phased arrays. The role requires extensive experience in photonic design and layout-including chip-level ownership of photonic circuit design for commercial foundry tapeouts-and deep expertise in spectral filter design and communication link budgets.
NewPrincipal Analog/Mixed-Signal ASIC Engineer Taara Connect IncPrincipal Analog/Mixed-Signal ASIC EngineerSunnyvale, CAThe role requires extensive experience in ASIC design and layout-including top-level ownership of ASIC tape-outs at leading commercial foundries-and deep expertise in either or both of these two categories: high-precision AMS circuits and high-speed wireline/silicon photonics interface circuits. High-speed designs: Front-end circuits for optical communication, including modulator drivers and transimpedance amplifiers (TIAs) operating at tens of GHz, and broadband circuits for serial links including receivers, transmitters, and equalizers.
NewSenior High-Speed Photonic Design Engineer Taara Connect IncSenior High-Speed Photonic Design EngineerSunnyvale, CATaara is seeking a Senior High-Speed Photonic Design Engineer to work on next-generation photonic and electronic integrated modules as part of the R&D team developing cutting-edge wireless optical communication systems based on integrated optical phased arrays. The successful candidate will own photonic transmitter and receiver architecture, high-speed photonic modulator and detector design, and RF/microwave transmission line design within the very-large-scale photonic integrated circuits (PICs) developed at Taara.