Electrical Engineering Digital Design Lead HDR, Inc.Electrical Engineering Digital Design LeadIrvine, CAOur eight Employee Network Groups (Asian Pacific, Black, Hispanic/Latino(a), LGBTQ, People with Disabilities, Veterans, Women, Young Professionals) help create a sense of belonging and foster a supportive environment where everyone is empowered to engage and contribute. At HDR, our employee-owners are fully engaged in creating a welcoming environment where each of us is valued and respected, a place where everyone is empowered to bring their authentic selves and novel ideas to work every day.
Senior Principal Digital Design Engineer MaxLinear, Inc.Senior Principal Digital Design EngineerIrvine, California$186,000–$228,000 / yearFull timeOne such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs. We are a fabless system-on-chip product company, striving to improve the world’s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications.
Design Verification Engineer (Silicon Engineering) SpaceXDesign Verification Engineer (Silicon Engineering)Irvine, CA$125,000–$145,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
NewSr. Soc/Asic Physical Design Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Soc/Asic Physical Design Engineer (Silicon Engineering)Irvine, CA$165,000–$260,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesDesign Verification Engineer (Silicon Engineering)Irvine, CA$125,000–$145,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
NewPhysical Design Engineer II (Silicon Engineering) Space Exploration TechnologiesPhysical Design Engineer II (Silicon Engineering)Irvine, CA$145,000–$195,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Manager, Asic Design Engineering (Starshield Silicon) Space Exploration TechnologiesManager, Asic Design Engineering (Starshield Silicon)Hawthorne, CA$190,000–$245,000 / yearThe Manager, ASIC Design Engineering will lead a team that develops ASICs and FPGAs for cutting edge satellites systems that deliver unprecedented quantities of data at unheard of speeds to the service-members who defend our Nation and Allies. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
ASIC / FPGA Digital Design Engineer - (Lead or Senior) The Boeing CoASIC / FPGA Digital Design Engineer - (Lead or Senior)Huntington Beach, CA$146,200–$197,800 / yearTypical Education/Experience: Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Programs may include next-generation satellite and space systems, modules supporting NASA missions, Space Launch System (SLS)-related technologies, commercial and military aircraft platforms, autonomous aviation technologies, and emerging digital architectures supporting future aerospace systems.
ASIC / FPGA Digital Design Engineer - (Associate or Experienced) The Boeing CoASIC / FPGA Digital Design Engineer - (Associate or Experienced)Huntington Beach, CA$98,600–$133,400 / yearBoeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/ FPGA Digital Design Engineers - (Associate or Experienced) to join us as part of our Boeing Electronic Products team at the heart of Boeing's products to support advanced digital subsystem development in an aerospace environment in El Segundo or Huntington Beach, CA. Programs may include next-generation satellite and space systems, modules supporting NASA missions, Space Launch System (SLS)-related technologies, commercial and military aircraft platforms, autonomous aviation technologies, and emerging digital architectures supporting future aerospace systems.
Principal Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesPrincipal Design Verification Engineer (Silicon Engineering)Irvine, CA$210,000–$335,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Sr. Digital Circuit Design Engineer OmnivisionSr. Digital Circuit Design EngineerIrvine, California$130,600–$160,000 / yearParticipate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs. Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related field, or equivalent practical experience.
Senior Staff Digital Design Engineer MarvellSenior Staff Digital Design EngineerIrvine, CAOur group architects and implements advanced digital pipelines, high speed datapaths, and DSP driven processing engines that enable ultra high bandwidth, low latency data movement across next generation Ethernet and optical interconnects. Strong background in high‑performance DSP and high‑speed datapath design, including pipelined arithmetic units, algorithm‑driven hardware implementation, packet processing engines, memory subsystems, and large‑scale control/state machines.
Digital Design Engineer MarvellDigital Design EngineerIrvine, CAHighlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
Digital Design Engineer Omnivision TechnologiesDigital Design EngineerIrvine, CA$110,600–$140,000 / yearParticipate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs. Minimum QualificationsBachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related field, or equivalent practical experience.
Principal, IC Digital Design Engineer MarvellPrincipal, IC Digital Design EngineerIrvine, CAOur group architects and implements advanced digital pipelines, high speed datapaths, and DSP driven processing engines that enable ultra high bandwidth, low latency data movement across next generation Ethernet and optical interconnects. Strong background in high‑performance DSP and high‑speed datapath design, including pipelined arithmetic units, algorithm‑driven hardware implementation, packet processing engines, memory subsystems, and large‑scale control/state machines.
Design Engineer 7848 Taiwan Semiconductor Manufacturing Co LtdDesign Engineer 7848California, CA$155,896–$156,000 / yearWork experience or academic coursework must have included: Experience in RTL coding, digital design and testing, physical implementation or design verification; Experience in Perl/TCL language programming; Experience with N16 and below technology; Experience with Chip level integration, and wire editing, Low-power implementation methodology; Experience with Netlist-GDS P&R, signoff task; Experience in block level implementation or chip integration and signoff; Knowledge of major EDA tools/design flows; and knowledge of hardware design including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation. Specific job duties include: DRC/LVS/ERC/ANTENNA analysis and clean up, Floorplan analysis and congestion solution; Power IR/EM analysis and fix; Signal EM/Noise analysis and fix; Physical verification sign off; Implement ECOs for timing closure; Customized Clock tree structure; May also perform floorplan, place and route.
Digital Design Engineer, Air Dominance and Strike Anduril Industries IncDigital Design Engineer, Air Dominance and StrikeCosta Mesa, CA$146,000–$194,000 / yearTo ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
Creative Operations Manager, Environmental Design Anduril Industries IncCreative Operations Manager, Environmental DesignCosta Mesa, CA$129,000–$171,000 / yearTo ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. This third-party service provider provides risk-intelligence services that may include analysis of sanctions and watchlists, adverse media, public-record information, and other lawful open-source or commercial data sources.
Digital Design Engineer (MPU) BrainChip Holdings LtdDigital Design Engineer (MPU)Laguna Hills, CAIf you enjoy building processors, working close to the hardware, and solving performance challenges for AI workloads, this is a strong fit. Were looking for a Digital Design Engineer to help design and implement the core compute architecture behind our next-generation systems.
RFIC - PLL Design Engineer Apple IncRFIC - PLL Design EngineerIrvine, CAOur wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by a best-in-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless connectivity solutions into hundreds of millions of products.