NewPrincipal Engineer, CAD SiTime CorporationPrincipal Engineer, CADSanta Clara, CA$148,320–$203,940 / yearResponsibilities include user support for Behavioral, RTL and Analog Designs, Schematics, Analog Mixed-Signal Simulations, IC Physical Design layout, CAD tool customizations, Linux Support, implementation and testing of new software tools and deploy new CAD Tool flows. The Principal CAD Engineer will also interface with EDA Tool Vendors and have responsibilities for implementation and performance testing of new software releases, prior to deploying to IC Designers across multiple engineering sites.
NewPrincipal Analog Mixed-Signal Design Engineer SiTime CorporationPrincipal Analog Mixed-Signal Design EngineerSanta Clara, CA$148,320–$203,940 / yearDetailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture. Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release.
NewPrincipal Hardware Signal Integrity / Power Integrity Architect SiTime CorporationPrincipal Hardware Signal Integrity / Power Integrity ArchitectSanta Clara, CA$148,320–$203,940 / yearThe Principal Hardware Signal Integrity/Power Integrity Architect is accountable for system-level electrical design and for establishing signal and power integrity simulation methodologies that underpin the development of hardware platforms used for validation, testing, and high-volume production of MEMS timing products. Establish comprehensive methodologies for both signal and power integrity across a variety of hardware platforms, including validation environments, probing stations, load boards, and production test systems.
NewSr. Staff Engineer, Mechanical Gener8, LLCSr. Staff Engineer, MechanicalSan Jose, CARegulatory Compliance: Author technical documentation for FDA submissions (510k, PMA) and international bodies, strictly following FDA Quality System Regulations (21 CFR Part 820) and ISO 13485. Since 2002, Gener8 has guided our customers by turning their innovative concepts into reality by providing engineering design services and manufacturing complex instruments, software, and consumables.
NewLead Mechanical Engineer HECO Pacific Manufacturing INCLead Mechanical EngineerUnion City, CAJob Description HECO PACIFIC Manufacturing, Inc. is engineering and manufacturing company located in Union City, CA, we build overhead bridge cranes from ¼ Ton to 300 Ton capacities. Quality Assurance : Ensure fabricated equipment meets NQA-1 and NOG-1 compliance, working closely with quality assurance teams.
Principal Engineer, Post-silicon Validation Ayar LabsPrincipal Engineer, Post-silicon ValidationSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Root Cause and Debug: Investigate and drive to closure all silicon failure modes, from signal integrity issues to mixed-signal anomalies, using systematic debug methodologies and close collaboration with design and firmware teams.
Principal Engineer, Design Verification - DDR Memory Subsystems Altera SemiconductorPrincipal Engineer, Design Verification - DDR Memory SubsystemsSan Jose, California$209,500–$299,200 / yearWith more than four decades of industry-leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, edge computing, and embedded systems. As a Principal Engineer, you'll have the opportunity to shape verification strategy across multiple product generations, influence architectural decisions, mentor world-class engineering teams, and solve some of the industry's most challenging memory subsystem verification problems.
Sr. Principal Engineer, SoC Architect Ayar LabsSr. Principal Engineer, SoC ArchitectSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Cross-Functional Collaboration Work closely with: Design and verification teams on implementation feasibility, Firmware/software teams on boot, drivers, and runtime optimization, Validation teams on bring-up and debug strategies and Product and business teams on roadmap alignment.
Sr. Principal Electrical Engineer, Microgrid Modeling BloomEnergySr. Principal Electrical Engineer, Microgrid ModelingSan Jose, CA$196,000–$282,000This position is intended for an engineer with deep domain expertise and extensive hands‑on experience in microgrid modeling and simulation, capable of independently evaluating complex systems and operating scenarios and delivering high‑confidence, model‑driven insights to support system design and validation. This role focuses on advanced electrical and dynamic modeling of inverter‑based resources, energy storage systems, generation assets, microgrid controllers, and distribution networks to ensure robust performance, stability, resilience, and compliance with project requirements and applicable grid codes.
Principal Engineer - AI and Compute Server Design Hyve SolutionsPrincipal Engineer - AI and Compute Server DesignFremont, CaliforniaTechnical expertise: Deep understanding of high-speed interfaces (PCIe Gen5/6, CXL, NVLink, Ethernet), power delivery networks, SI/PDN design, thermal considerations, and complex multi-board systems; demonstrated success leading EVT/DVT/PVT validation and manufacturing ramp. As a Principal Engineer on the AI and Compute Server Design team, you will own the end-to-end hardware design of next-generation GPU and compute servers and help build the platforms that power the next generation of AI infrastructure.
Principal Engineer, Product Compliance BloomEnergyPrincipal Engineer, Product ComplianceSan Jose, CA$176,300–$253,700Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm. For over two decades, we’ve been at the forefront of the global energy transition, pioneering solutions that empower critical industries to thrive in a rapidly digitizing, energy-intensive world.
Sr Principal Engineer, Enclosures Design BloomEnergySr Principal Engineer, Enclosures DesignSan Jose, CA$196,000–$282,000They have experience in the automotive industry having delivered cars and trucks to the vehicle marketplace, or in NEMA 4X compliant enclosures, sealing strategies and manufacturing approaches that survive real world deployment for decades. Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm.
Principal Engineer, Analog Design Lumentum Inc.Principal Engineer, Analog DesignSan Jose, CALumentum is seeking a highly experienced and technically proficient Principal Engineer, Analog Design to lead the design, development, and validation of complex analog circuits for cutting-edge optical communication products. With our continual goal of making Lumentum a best place to work for our employees, we strive to offer employees competitive total compensation packages, which may include annual bonus, commission for certain sales roles, equity, and health and welfare benefits.
Principal Engineer - Standard Cell Design Intel Corp.Principal Engineer - Standard Cell DesignSanta Clara, CA$220,920–$311,890 / yearBusiness group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Principal Engineer, AI System Architect (Hardware) Samsung SemiconductorPrincipal Engineer, AI System Architect (Hardware)San Jose, CA$219,000–$351,000 / yearAnalyze representative and emerging system-level architectural research (e.g., LLMs, DLRMs, and future AI models) to derive architecture requirements and trade-offs across compute, memory, networking, and power. In this role, you will develop system-level performance models, drive architecture-level design decisions, and propose forward-looking AI system architectures that shape Samsung's long-term AI platform strategy.
Principal Engineer, SerDes AMS Design and Architecture Ayar LabsPrincipal Engineer, SerDes AMS Design and ArchitectureSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Key Responsibilities: Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
Principal Engineer, Electronic Hardware Design Ayar LabsPrincipal Engineer, Electronic Hardware DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
Principal Engineer, SerDes Validation Ayar LabsPrincipal Engineer, SerDes ValidationSan Jose, CaliforniaDrive Product Bring-up: Collaborate with Design Engineering to bring up cutting-edge silicon photonic and laser products, troubleshooting and resolving complex technical issues on the optical SerDes devices. Lead New Product Introduction (NPI): Collaborate with multi-disciplinary teams to identify and implement product improvements through bench characterization and ensure successful transition of products from development to mass production.
Principal Electrical Engineer - (99105.1) SanminaPrincipal Electrical Engineer - (99105.1)San Jose, CA$150,000–$200,000 / yearThe total rewards package also includes a variety of benefits, including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business and, depending on the role, may include eligibility for restricted stock unit awards and participation in a discretionary bonus program. VES also designs and builds NVMe flash based server appliances, JBOD storage systems and related products for a variety of data center and storage applications.
Senior Principal Engineer, Hardware Application Engineering Board & System Design Veracity Software IncSenior Principal Engineer, Hardware Application Engineering Board & System DesignSanta Clara, CAMotivation / Reason for Relocation (if not local): Motivation / Reason for Interest in this Position: Contact Number: Email ID: LinkedIn Profile URL: Current Location (City, State): Full Address (Street, City, State, ZIP Code): Current Work Authorization Status: Expected Salary: Notice Period: Are you willing to relocate on your own expense and work onsite in Santa Clara, California? Full Name: Highest Education (Institution, Degree & Graduation Year): Total Years of Hardware Design Experience: Total Years of Board & System Design Experience: Do you have at least 15 years of experience in hardware design, development, and validation of high-speed networking or compute systems?