Principal Engineer, Analog Design Lumentum Inc.Principal Engineer, Analog DesignSan Jose, CALumentum is seeking a highly experienced and technically proficient Principal Engineer, Analog Design to lead the design, development, and validation of complex analog circuits for cutting-edge optical communication products. With our continual goal of making Lumentum a best place to work for our employees, we strive to offer employees competitive total compensation packages, which may include annual bonus, commission for certain sales roles, equity, and health and welfare benefits.
Senior Principal Engineer, Offensive Security Astera LabsSenior Principal Engineer, Offensive SecuritySan Jose, CA$190,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Principal Engineer, Security Architect Astera LabsSenior Principal Engineer, Security ArchitectSan Jose, CA$190,000–$240,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Principal Engineer, Hardware Application Engineering Signal Integrity & Power Integrity Veracity Software IncSenior Principal Engineer, Hardware Application Engineering Signal Integrity & Power IntegritySanta Clara, CAFull Name: Highest Education (Institution, Degree & Graduation Year): Total Years of Hardware Design Experience: Total Years of Signal Integrity (SI) Experience: Total Years of Power Integrity (PI) Experience: Do you have at least 15 years of experience in hardware design, development, and validation of high-speed networking or compute systems? Motivation / Reason for Relocation (if not local): Motivation / Reason for Interest in this Position: Contact Number: Email ID: LinkedIn Profile URL: Current Location (City, State): Full Address (Street, City, State, ZIP Code): Current Work Authorization Status: Expected Salary: Notice Period: Are you willing to relocate on your own expenses to Santa Clara, CA and work onsite?
Senior Principal Engineer, Hardware Application Engineering Board & System Design Veracity Software IncSenior Principal Engineer, Hardware Application Engineering Board & System DesignSanta Clara, CAMotivation / Reason for Relocation (if not local): Motivation / Reason for Interest in this Position: Contact Number: Email ID: LinkedIn Profile URL: Current Location (City, State): Full Address (Street, City, State, ZIP Code): Current Work Authorization Status: Expected Salary: Notice Period: Are you willing to relocate on your own expense and work onsite in Santa Clara, California? Full Name: Highest Education (Institution, Degree & Graduation Year): Total Years of Hardware Design Experience: Total Years of Board & System Design Experience: Do you have at least 15 years of experience in hardware design, development, and validation of high-speed networking or compute systems?
IP Release Principal Engineer MarvellIP Release Principal EngineerSanta Clara, CAOwn and execute the IP delivery checklist at each milestone (iRTL, Code Complete, RTLF), verifying completeness of all required collateral including: RTL source files, file manifests (.f/.vc), SDC, UPF, memory lists, CDC crossing lists, static waivers, CSR/register descriptions, synthesis scripts, and integration guidelines. Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree.
Senior Principal Engineer, Hardware Application Engineering — Board & System Design MarvellSenior Principal Engineer, Hardware Application Engineering — Board & System DesignSanta Clara, CaliforniaYou will spend most of your time reviewing and shaping customer hardware designs — covering board architecture, PCB stack-up and material selection, power architecture, thermal design, mechanical integration, and reliability and retain full hands-on capability across the entire design lifecycle from architecture through schematic, layout guidance, and bring-up. As Senior Principal Engineer for Board & System Hardware Design, you will be the senior technical authority guiding customer hardware design-in on Marvell's Ethernet Switch and UALink platforms, and a key technical bridge between Marvell's silicon teams, internal hardware engineering, and the field.
Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity MarvellSenior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power IntegritySanta Clara, CaliforniaYou will own layout guideline definition, post-silicon channel extraction and simulation, compliance testing, and SerDes tuning guidance, while also reviewing customer PDN designs and feeding learnings back to Marvell's silicon and hardware engineering teams as part of a continuous improvement loop. Note on experience level: While the years of experience above represent the typical bar for this role, exceptionally talented candidates with fewer years but demonstrated mastery — through impactful project work, deep technical contributions, or industry recognition — are strongly encouraged to apply.
Senior Principal Engineer, Micro-Architecture And RTL MarvellSenior Principal Engineer, Micro-Architecture And RTLSanta Clara, CAParticipate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Principal Engineer, Mapping And Localization PlusAI Inc.Principal Engineer, Mapping And LocalizationSanta Clara, CA$200,000–$260,000 / yearDesign and implement robust, real-time algorithms for sensor fusion, visual/LiDAR odometry, and global localization using techniques like Factor Graphs, EKF/UKF, and particle filters. You will tackle the hardest edge cases-from GPS-denied tunnels to dynamic construction zones-ensuring our vehicles operate safely in complex L4 ODDs (Operational Design Domains).
Principal Engineer, Power Electronics Graphcore Ltd.Principal Engineer, Power ElectronicsMilpitas, CAWork with vendors to ensure their planned future technologies are pulled into our system engineering roadmap AND ensure that our (system engineering) required technological innovation is being driven into their (power vendor) roadmap. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. .
Sr. Principal Electrical Engineer, Microgrid Modeling BloomEnergySr. Principal Electrical Engineer, Microgrid ModelingSan Jose, CA$196,000–$282,000This position is intended for an engineer with deep domain expertise and extensive hands‑on experience in microgrid modeling and simulation, capable of independently evaluating complex systems and operating scenarios and delivering high‑confidence, model‑driven insights to support system design and validation. This role focuses on advanced electrical and dynamic modeling of inverter‑based resources, energy storage systems, generation assets, microgrid controllers, and distribution networks to ensure robust performance, stability, resilience, and compliance with project requirements and applicable grid codes.
Principal Engineer - AI and Compute Server Design Hyve SolutionsPrincipal Engineer - AI and Compute Server DesignFremont, CaliforniaTechnical expertise: Deep understanding of high-speed interfaces (PCIe Gen5/6, CXL, NVLink, Ethernet), power delivery networks, SI/PDN design, thermal considerations, and complex multi-board systems; demonstrated success leading EVT/DVT/PVT validation and manufacturing ramp. As a Principal Engineer on the AI and Compute Server Design team, you will own the end-to-end hardware design of next-generation GPU and compute servers and help build the platforms that power the next generation of AI infrastructure.
Sr Principal Engineer, Enclosures Design BloomEnergySr Principal Engineer, Enclosures DesignSan Jose, CA$196,000–$282,000They have experience in the automotive industry having delivered cars and trucks to the vehicle marketplace, or in NEMA 4X compliant enclosures, sealing strategies and manufacturing approaches that survive real world deployment for decades. Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm.
Principal Engineer, Product Compliance BloomEnergyPrincipal Engineer, Product ComplianceSan Jose, CA$176,300–$253,700Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm. For over two decades, we’ve been at the forefront of the global energy transition, pioneering solutions that empower critical industries to thrive in a rapidly digitizing, energy-intensive world.
Principal Engineer, Post-silicon Validation Ayar LabsPrincipal Engineer, Post-silicon ValidationSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Root Cause and Debug: Investigate and drive to closure all silicon failure modes, from signal integrity issues to mixed-signal anomalies, using systematic debug methodologies and close collaboration with design and firmware teams.
Senior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & Optimization Altera SemiconductorSenior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & OptimizationSan Jose, CaliforniaIn this role, you will play a critical leadership position in shaping the future of the Quartus FPGA Compiler , driving innovations in timing analysis, modeling, optimization, and timing closure technologies that help customers achieve faster compilation, improved QoR, and more predictable design convergence on next-generation FPGA platforms. Altera is seeking a highly experienced Senior Principal Engineer / Subject Matter Expert (SME) to drive the architecture, development, and advancement of next-generation timing analysis, modeling, and optimization technologies within the Quartus FPGA Compiler .
Senior Principal Engineer, Software / Firmware Veracity Software IncSenior Principal Engineer, Software / FirmwareSanta Clara, CAThe successful candidate will serve as a subject matter expert for next-generation coherent optical modules, including 400ZR, 400ZR+, and 800ZR platforms, while contributing to Common Platform Optics (CPO) initiatives and advanced optical networking solutions. This role will drive firmware strategy, architecture, implementation, validation, and production release while collaborating closely with hardware, DSP, test, manufacturing, and customer engineering teams.
Principal Engineer - Standard Cell Design Intel Corp.Principal Engineer - Standard Cell DesignSanta Clara, CA$220,920–$311,890 / yearBusiness group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Principal Engineer, Design Verification - DDR Memory Subsystems Altera SemiconductorPrincipal Engineer, Design Verification - DDR Memory SubsystemsSan Jose, California$209,500–$299,200 / yearWith more than four decades of industry-leading FPGA expertise, our singular mission is to deliver programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets including AI, cloud, networking, edge computing, and embedded systems. As a Principal Engineer, you'll have the opportunity to shape verification strategy across multiple product generations, influence architectural decisions, mentor world-class engineering teams, and solve some of the industry's most challenging memory subsystem verification problems.