Device and buffer architecture: Define requirements for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, future buffer architectures, and supporting components, including partitioning, topology, interfaces, protocols, clocking, performance, power, training, telemetry, reliability, security, test, error handling, recovery, and interoperability. This architect will define AMD’s multi-generation LPDDR and DRAM-buffer roadmap; lead technical positions for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, and future buffer architectures; and represent AMD in JEDEC and the broader memory ecosystem.