San Diego, CA30+ days ago
Perform RTL design, synthesis, LINT, RDC/CDC, LEC, timing constraint development, static timing analysis for digital control logic, which includes off-chip and on-chip serial bus, interface to analog blocks, clock distribution, AMBA bus, state machine, memories, embedded processor cores (RISC-V), bus arbitration, DMA, registers, IO pads, synchronous, asynchronous access and control functions. In depth knowledge and extensive hands-on experience in digital RTL design (Verilog/System Verilog) and micro-architecture, linting, LEC, RDC/CDC, SDF gate simulation, revision control and tagged releases, scripting, bug tracking, synthesis, scan insertion, timing constraint development, floor planning, clock tree synthesis, timing closure, netlist ECOs, and digital verification.