Senior Silicon Physical Design and Layout Engineer Blue Origin Enterprises LPSenior Silicon Physical Design and Layout EngineerSan Francisco, CA$197,529–$276,539.55 / yearand/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
Digital IC Design Engineer Intern NeuralinkDigital IC Design Engineer InternSouth San Francisco, CAJob Description and Responsibilities: We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces.
Design Verification Lead Advanced Micro Devices IncDesign Verification LeadSan Jose, CAAs a member of the front-end design and integration team, you will collaborate closely with architecture, IP design, physical design, firmware, and product engineering teams to deliver first-pass silicon success for next-generation PCIe and CXL-based IP solutions. KEY RESPONSIBILITIES: Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
Technical Lead, Custom Digital Circuit Design, Mixed Signal Google LLCTechnical Lead, Custom Digital Circuit Design, Mixed SignalSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving team behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
PMTS ASIC Digital Design IP ENGINEERING GlobalFoundries IncPMTS ASIC Digital Design IP ENGINEERINGSanta Clara, CA$167,000–$275,000 / yearSummary of Role: The PMTS Digital Design Engineer will lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components. About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies.
RF/Analog Mixed Signal Design Engineer Apple IncRF/Analog Mixed Signal Design EngineerSunnyvale, CAAs a team, we will be working on the leading-edge technology nodes to build elite custom analog designs used to connect our world-class products to the physical world as well as enable optimizing their performance. Solid understanding/experience in bandgaps, bias, opamps, switched-cap circuits, LDOs, low power oscillators, PLLs, VGAs, feedback and compensation techniques.
Senior Engineer, GPU RTL Design - Pixel Pipe Samsung Electronics America IncSenior Engineer, GPU RTL Design - Pixel PipeSan Jose, CA$139,000–$208,400 / yearYou support technical excellence by driving design quality and accuracy, developing clean, synthesizable RTL, and collaborating with verification teams to enable thorough validation, resolve functional issues, and ensure coverage, robustness, and sustainability across complex graphics processing flows. In this mid-to-senior individual contributor role, you will collaborate closely with hardware and software design teams and work across multiple GPU functional domains-including control, datapath, memory systems, and fixed-function logic, with a focus on pixel processing and graphics pipeline stages.
ASIC Design Verification Technical Lead, High-Speed DSP Google LLCASIC Design Verification Technical Lead, High-Speed DSPSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
RTL / Circuit IP Design Engineer Advanced Micro Devices IncRTL / Circuit IP Design EngineerSan Jose, CATHE ROLE: The focus of this role is to plan, build, and execute the implementation of new and existing features for AMD's programmable embedded IP, resulting in final designs that meet product defined power, performance, and area targets with intended functionality that operates on silicon and is modeled accurately for customer design use. Strong understanding of circuit design concepts, translating circuit designs in an optimal way to either custom implementations or with best practices for RTL synthesis.
Engineering Associate I (Engineering Drafter) - Project Design & Development - San Francisco Public Works (5364) City and County of San FranciscoEngineering Associate I (Engineering Drafter) - Project Design & Development - San Francisco Public Works (5364)San Francisco, CAThe staff designs and manages the construction of civic buildings and streets; cleans and greens the right of way; maintains civic buildings; manages multi-million-dollar bond programs; trains people for jobs; keeps the right of way free of hazards; paves the roads; repairs bridges and public stairways; expands accessibility; and works at the forefront addressing some of San Francisco's biggest challenges. MINIMUM QUALIFICATIONSExperience: Four (4) years of verified civil (including structural /or transportation) technical engineering drafting experience using CAD or BIM systems to prepare engineering drawings and other engineering graphic material, at least two (2) years of which must have been in a position with duties comparable to those of Class 5362 Engineering Assistant.
Senior Design Verification Engineer ProteanTecs Ltd.Senior Design Verification EngineerSanta Clara, CAWhy proteanTecs is a great place to work: Fast-paced and impactful: We"re a mission-driven startup, so you"ll tackle new challenges daily, wear many hats, and see your work directly influence the future of electronics. We are looking for a We are looking for a Senior Design Verification Engineer to join a global team of Application Engineers that own the technical success and customer satisfaction across multiple high-impact projects.
Hardware Design Engineer Apple IncHardware Design EngineerSunnyvale, CAProven track record of leading project teams to complete projects or key components of the project 5+ years of experience delivering consumer electronic products is preferred Experience in architectural discussion with cross-functional leaders related to Power supply and Digital design for the connectivity HW and able to influence product direction for these designs Experience with power supply/power management Hands on debug experience with usage of modern lab equipment (DSOs, Logic Analyzers, Protocol Analyzers) Experience in writing basic software routines and test scripts Strong desire to investigation system level issues and drive problems to closure in a team-based environment with a proactive demeanor Experience with mobile and/or embedded processors and memory systems Experience with schematic capture/layout Experience interacting with offshore manufacturing partners Successful track record of delivering highly innovative communications products Experience with high volume, low power, mobile products. Implement in-product schematics and layout Work with internal hardware and silicon teams to bring-up, characterize (performance/power) and validate new digital interfaces + protocols Work with power supply application circuit design and validation, including load step response, ripple and accuracy, stability Work with external chipset vendors to develop successful integration and verification plans Be required to travel internationally as needed (~15%)BS and 10+ years of relevant industry experience Good understanding of protocol specifications for communication interfaces like PCIe, MIPI, I2C, SPI, UART, etc.
Senior ASIC Design Verification Engineer, Cloud Google LLCSenior ASIC Design Verification Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Senior CAD Engineer, RTL Design, Silicon, Google Cloud Google LLCSenior CAD Engineer, RTL Design, Silicon, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
SoC Design Verification Engineer Advanced Micro Devices IncSoC Design Verification EngineerSan Jose, CAWhether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
Principal Design Lead Intuit IncPrincipal Design LeadMountain View, CA$220,500–$298,500 / yearJoining the CEO Transformation Office means working on the company's most visible, mission-critical initiatives, partnering with senior leaders across the business, and helping define how Intuit's strategy is experienced by the world. Creative Partnership: Act as a strategic conceptual partner to other creative leads across copy, video, motion design, providing the graphic depth and quality needed for award-winning work.
Sr. Staff GaN Device Design Engineer Alpha and Omega Semiconductor LimitedSr. Staff GaN Device Design EngineerSunnyvale, CAAt Alpha and Omega Semiconductor (AOS), we design, develop and globally supply a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM, TVS, GaN/SiC, Power IC and Digital Power products. You will find our products in everyday applications including personal computers, graphic cards, gaming consoles, TVs, home appliances, smart phones, power tools, and more!
Visual Design Specialist - Fully Remote MercorVisual Design Specialist - Fully RemoteSan Francisco, CaliforniaRemote$80–$150 / hourDesign precise, task-specific grading criteria for real-world design deliverables such as brand identity systems and guidelines, campaign visuals, and packaging concepts. Background at world-class design studios or creative agencies, or in senior design roles at leading consumer or technology brands.
Behavioral Health Design Leader DLR GroupBehavioral Health Design LeaderSan Francisco, CA$140,000–$170,000 / yearAs a nationally recognized expert in Justice + Civic facility planning and design, DLR Group serves municipal, county, state, and federal public-sector clients to deliver civic, public safety, and justice design solutions that achieve excellence in operations, sustainable design, resilience planning, space planning, building assessment, cost of ownership analysis, and project management. As stewards of the built environment, DLR Group's Justice + Civic practice elevates behavioral, environmental, and social betterment, resulting in healing, equity, and transformation for the individual and community.
Staff Brand Designer AssuredStaff Brand DesignerPalo Alto, CaliforniaThe challenges we face are deep and diverse, from creating digital experiences that provide comfort and clarity to claimants at their most stressed and vulnerable to orchestrating large-scale ML-driven decision-making on billions of dollars of claims payments, life at Assured is dynamic, collaborative, and rewarding. Collaborate with web developers, 3D artists, motion designers, graphic designers, copywriters, sound designers and stakeholders on delivering high quality designs and bring ideas to life.