AI in Business, Postdoctoral Research Fellow San Diego State UniversityAI in Business, Postdoctoral Research FellowSan Diego, CaliforniaCurrent projects include behavioral modeling for mental health indicators, educational support through goal-directed robot communication, self-supervised speech and audio modeling, and the development of robots capable of interpreting and responding to verbal and nonverbal signals. As a higher education institution, we are dedicated to advancing knowledge and empowering individuals to reach their full potential by prioritizing inclusive curriculum development, faculty and staff training, student mentorship, and comprehensive support programs.
Senior Product Manager, Fortary - Remote Ava LabsSenior Product Manager, Fortary - RemoteSan Diego, CARemoteAs the business architect for trading, lending, and liquidity, the Senior Product Manager will define and lead the long-term product vision, portfolio strategy, and investment priorities for Fortarys institutional trading, lending, and liquidity platform, ensuring alignment with company objectives and growth strategy. The ideal candidate brings a proven track record of defining and scaling successful B2B fintech or digital asset products, shaping long-term product strategy, and leading complex cross-functional initiatives.
Department of Management Information Systems Lecturer Pool 2026-2027 San Diego State UniversityDepartment of Management Information Systems Lecturer Pool 2026-2027San Diego, CaliforniaRequired: Please mark subjects available to teach -- database, AI, cybersecurity, data science/statistics, operations management/supply chain, python programming, computer networking, systems admin, digital innovation, systems analysis & design. Pursuant to Education Code 89521, the California State University requires that employment applicants disclose any final administrative decision or final judicial decision issued within the last seven years determining that the applicant committed sexual harassment.
Software Engineer II - TS w/ SCI eligibility Parsons CorpSoftware Engineer II - TS w/ SCI eligibilitySan Diego, CA$103,500–$181,100 / yearWe have built this cultural legacy by working closely with analysts and operators to understand their needs and delivering meaningful value through innovative, cost effective and intuitive software solutions. Minimum of 5+ years of software development experience with a bachelor's degree in computer science or other technical discipline (additional years of experience may be considered in lieu of degree).
Software Engineer Parsons Commercial Technology Group Inc.Software EngineerSan Diego, CA$74,800–$130,900 / yearWe have built this cultural legacy by working closely with analysts and operators to understand their needs and delivering meaningful value through innovative, cost effective and intuitive software solutions. Minimum of 3+ years of software development experience with a bachelor's degree in computer science or other technical discipline (additional years of experience may be considered in lieu of degree).
Software Engineer Parsons CorpSoftware EngineerSan Diego, CA$74,800–$130,900 / yearWe have built this cultural legacy by working closely with analysts and operators to understand their needs and delivering meaningful value through innovative, cost effective and intuitive software solutions. Minimum of 3+ years of software development experience with a bachelor's degree in computer science or other technical discipline (additional years of experience may be considered in lieu of degree).
Staff Engineer, ASIC/VLSI Synthesis and Design Marvell Technology IncStaff Engineer, ASIC/VLSI Synthesis and DesignSan Diego, CABachelor's degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows.
Principal Engineer, ASIC/VLSI Synthesis and Design Marvell Technology IncPrincipal Engineer, ASIC/VLSI Synthesis and DesignSan Diego, CABachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows.
Senior Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis Marvell Technology IncSenior Staff Engineer, ASIC Design/Implementation - LEC/STA/Power AnalysisSan Diego, CAThey should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
Principal Hardware Engineer, Optics Marvell Technology IncPrincipal Hardware Engineer, OpticsSan Diego, CABachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Principal Engineer, Asic/Vlsi Synthesis And Design MarvellPrincipal Engineer, Asic/Vlsi Synthesis And DesignSan Diego, CABachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows.
Principal Engineer, Asic Design/Implementation - Lec/Sta/Power Analysis MarvellPrincipal Engineer, Asic Design/Implementation - Lec/Sta/Power AnalysisSan Diego, CAThey should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
Principal Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis Marvell Technology IncPrincipal Engineer, ASIC Design/Implementation - LEC/STA/Power AnalysisSan Diego, CAThey should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
Senior Staff Engineer, Asic/Vlsi Synthesis And Design MarvellSenior Staff Engineer, Asic/Vlsi Synthesis And DesignSan Diego, CACollaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
Senior Staff Engineer, Asic Design/Implementation -- Lec/Sta/Power Analysis MarvellSenior Staff Engineer, Asic Design/Implementation -- Lec/Sta/Power AnalysisSan Diego, CAThey should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
Senior Staff Engineer, Asic Design/Implementation - Lec/Sta/Power Analysis MarvellSenior Staff Engineer, Asic Design/Implementation - Lec/Sta/Power AnalysisSan Diego, CAThey should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
Staff Engineer, Asic Design/Implementation - Lec/Sta/Power Analysis MarvellStaff Engineer, Asic Design/Implementation - Lec/Sta/Power AnalysisSan Diego, CAThey should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. Bachelor's degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.
Staff Engineer, ASIC Design/Implementation - LEC/STA/Power Analysis Marvell Technology IncStaff Engineer, ASIC Design/Implementation - LEC/STA/Power AnalysisSan Diego, CAThey should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs. Bachelor's degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.
Senior Staff Engineer, ASIC/VLSI Synthesis and Design Marvell Technology IncSenior Staff Engineer, ASIC/VLSI Synthesis and DesignSan Diego, CACollaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for synthesis, PnR and chip timing sign-off flows. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
NewSenior Software Product Owner AbbottSenior Software Product OwnerLa Jolla, CaliforniaThis position requires significant experience and technical knowledge in developing complex and sophisticated clinical genomics software and proven success driving software development initiatives by collaborating with cross-functional team members (Clinical Development, Laboratory Operations, Medical Affairs, Bioinformatics, Engineer, etc.) to ensure software product meet user and business needs. Software Product Owner works in a highly dynamic environment, engaging and coordinating the activities with internal stakeholders, enterprise architects, software developers, quality assurance, customer experience, contractors, and third-party vendors to drive flawless development of critical software products.