NewASIC/SoC Design Engineer Advanced Micro Devices, IncASIC/SoC Design EngineerSan Jose, CaliforniaDrive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
Analog And Mixed Signal Design Engineer Intel Corp.Analog And Mixed Signal Design EngineerSanta Clara, CA$164,470–$269,100 / yearPreferred Qualifications: Experience in one or more of the following areas is preferred: GPIOs, high speed parallel or serial IO links and their subcomponents (data path, TX, RX, etc.), clock distribution, clock conditioning, clock recovery circuits, voltage regulators, voltage reference circuits, ADCs/DACs, inductors, transmission lines, RF and millimeter-wave circuits, test of custom analog and mixed-signal circuits. Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly.
Product Design Engineer, AI Employee Experience: 26-01541 Akraya Inc.Product Design Engineer, AI Employee Experience: 26-01541San Francisco, CARemote$80–$90 / hourMost recently, we were recognized Stevie Employer of the Year 2025, SIA Best Staffing Firm to work for 2025, Inc 5000 Best Workspaces in US (2025 & 2024) and Glassdoor's Best Places to Work (2023 & 2022)! This role requires experience in designing internal tools for non-technical end users, with a focus on delivering consumer-grade product quality.
Sr. Staff/Staff Engineer, Digital Design InnoPhase IoTSr. Staff/Staff Engineer, Digital DesignSan Jose, CAIf you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you'll find your playground at Innophase IoT. In addition to delivering high quality digital solutions, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing.
Sr. Staff/Principal Engineer, Digital Design (San Diego) InnoPhase IoTSr. Staff/Principal Engineer, Digital Design (San Diego)San Jose, CAIf you are keen to work with a bunch of brilliant people with various backgrounds, if you share the same value of working smart and celebrating successes, if you have enthusiasm for big technology in a small company, if your goals are to learn and experience different aspects of work--not just singing the same song every day, you'll find your playground at Innophase IoT. In addition to delivering high quality digital solutions in the context of the product architecture, the team supports other disciplines with work product such as Verilog stimulus files, test benches for device bring up/characterization, test vectors for product manufacturing, etc.
Sr. Quality Engineer Karwell TechnologiesSr. Quality EngineerSanta Clara, CAMedical Device, ISO 13485, FDA, 21 CFR Part 820, CAPA, NC, Complaint Handling, Post Market Surveillance, PMS, MDR, MDD, Risk Management, ISO 14971, FMEA, DOE, QMS, IQ/OQ/PQ, Regulatory Compliance, Quality Engineer, Medical Device Quality. The ideal candidate will have hands-on experience in quality systems, risk management, complaint handling, post-market surveillance, and regulatory compliance within the medical device industry.
Design Engineer Chai DiscoveryDesign EngineerSan Francisco, CaliforniaThe ability to build what you design: comfortable moving from sketch to Figma to interactive prototype to production front-end code, and fluent talking code with engineers. A clear communicator who can articulate design decisions and synthesize complex science for cross-functional audiences, and a sharp listener who pulls the best ideas and the smallest details into the work.
Senior Design Engineer readyon.aiSenior Design EngineerSan Francisco, CaliforniaReadyOn is an AI-native labor operating system, built from the ground up for AI agents to perform real-time labor optimization—much like ridesharing platforms that match drivers and riders in real time, but applied to frontline labor instead of fixed, one-size-fits-all schedules. In this highly collaborative role, you'll empower our design and engineering teams to create consistently high-quality experiences across all products and platforms.
Senior Transmission Design Engineer Astro MechanicaSenior Transmission Design EngineerSan Francisco, CaliforniaTo achieve this, we are integrating our advanced airframe and engine technologies—which include Duality, our proprietary dual-use propulsion system—with a new flight operations model to make supersonic transport as efficient and economical as commercial air travel is today. Architect high-performance, high-speed geartrain systems with consideration for high-speed rotordynamic effects, lubrication, and highly integrated interfaces.
Senior Photonic Circuits Design Engineer TaaraSenior Photonic Circuits Design EngineerSunnyvale, CaliforniaTaara is seeking a Senior Photonic Circuits Design Engineer to work on next-generation photonic and electronic integrated modules as part of the R&D team developing cutting-edge wireless optical communication systems based on integrated optical phased arrays. The role requires extensive experience in photonic design and layout—including chip-level ownership of photonic circuit design for commercial foundry tapeouts—and deep expertise in spectral filter design and communication link budgets.
Design Engineer Retell AIDesign EngineerRedwood City, CaliforniaInstead of basic automation that needs constant human tuning, we're creating intelligent AI “workers” that act as frontline agents, QA analysts, and managers, continuously executing, monitoring, and improving every customer interaction. We're growing fast and looking for ambitious builders who want to tackle hard technical problems, move quickly, and have a real impact on one of the fastest-growing voice AI companies in the world.
Principle Design Engineer (ADC expertise) Monolithic Power SystemsPrinciple Design Engineer (ADC expertise)San Jose, CaliforniaAs a Principal design engineer, you will be responsible for the full cycle of our high-resolution ADC products, from architecture to design, simulation, layout supervision and post-layout verification. Self-motivated , willing to learn new technologies, & capable of working effectively within a group of individuals across multiple disciplines.
Analog/Mixed-Signal Circuit Design Engineer SK hynix AmericaAnalog/Mixed-Signal Circuit Design EngineerSan Jose, California$150,000–$250,000 / yearJob Title: Analog/Mixed-Signal Circuit Design Engineer Office Location: San Jose, CA Job Type: Full-Time Work Model: Onsite About SK hynix America At SK hynix America, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. BS in Electrical Engineering or a related field plus minimum 4 years of industry experience in analog and/or mixed-signal circuit design (or MS plus minimum 2 years of industry experience).
Physical Design Engineer - Block Level, Subsystem Implementation EtchedPhysical Design Engineer - Block Level, Subsystem ImplementationSan Jose, CaliforniaYou will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market. Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis.
Senior Staff RTL Design Engineer - CPU Frontend SiFiveSenior Staff RTL Design Engineer - CPU FrontendSanta Clara, California$205,740–$251,460 / yearSiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. United States of America Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
Physical Design Engineer EtchedPhysical Design EngineerSan Jose, Californiawill own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed. Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis.
Sr. Power Module Design Engineer Monolithic Power SystemsSr. Power Module Design EngineerSan Jose, CaliforniaWork with design engineers, field applications team, and TME to define new power module and IC products in DC/DC power solutions for industrial market. Responsibilities include defining high current density 48V/12V/5V DC/DC power module products, for applications including networking, optical and industrials, etc.
Platform Technologies Language & Frontend Design Engineer SiFivePlatform Technologies Language & Frontend Design EngineerBerkeley, CA$139,752–$170,808 / yearSiFive's unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. You will participate in the open source Chisel ( https://www.chisel-lang.org/ ) and CIRCT ( https://github.com/llvm/circt ) communities while ensuring that SiFive engineers have the best tools to build and verify advanced RISC-V CPUs, IPs, and SoCs.
TPU SoC Design Engineer, Cloud GoogleTPU SoC Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewDesign Engineer RilletDesign EngineerSan Francisco, CaliforniaTogether, we combine the precision of accounting with the speed, creativity, and ambition of AI-native software to power the financial core of the world’s fastest-growing companies while redefining what finance teams should expect from their software. Drive Rillet’s platform refresh across core surfaces like the launchpad, side nav, login, navigation patterns, empty states, tables, workflows, and other high-frequency product experiences.