SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire design verification landscape - including Unified Metric-Driven Verification (MDV), System Verilog (SV)/UVM-based methodologies, Mixed-Signal DV, Post-Silicon Validation Shift-Left, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation/Prototyping technologies. In this role, you will leverage your knowledge in Integrated Circuit (IC) design and verification with working knowledge of AI/ML to develop, integrate, deploy, and support best-in-class Agentic AI solutions including custom instructions, skills and automation scripts.