ASIC Design Engineer Intern (Video Silicon IP) - 2027 Summer

About the team Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.

We are looking for talented individuals to join us for an internship. Our internship program offers students hands-on experience, industry exposure, and opportunities to apply their knowledge to real-world challenges while building a strong foundation for personal and professional growth. Interns will gain practical experience, explore potential career paths, and participate in social events, learning programs, and development workshops alongside industry professionals. Candidates may apply to a maximum of two positions across Our Company and its affiliates globally. Applications will be considered in the order they are submitted. Applications are reviewed on a rolling basis, so we encourage you to apply early. Please clearly state your availability in your resume, including your start and end dates.

Responsibilities

• As an ASIC Design Engineer in this Video Silicon IP team, we work closely with architecture, algorithm and verification teams to build high performance and low power video processing IPs. Apply your knowledge of computer architecture and ASIC design to create ASIC design for compressing, processing still images and videos.Minimum Qualifications
• Currently pursuing an Undergraduate in computer science/electrical engineering or a related technical discipline
• Knowledge of Video Codecs
• Experience with RTL design (SystemVerilog) or High level Synthesis (HLS)
• Experience with UVM methodology, SystemC, or DPI
• Good programming skills in Python for task automation

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