Design Engineer

Payrate: $82.00- $85.00/hr.
 
Summary
Design Verification engineer for wearables silicon accelerator IPs testbench development, coverage-driven verification, RTL debug, and power/performance measurement.
 
Responsibilities

• Develop and execute verification plans for RTL blocks/IPs across the subsystem.
• Build and maintain System Verilog/UVM test benches; write directed and constrained-random tests.
• Drive functional coverage and assertion (SVA) closure; run and triage regressions.
• Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
• Build power/perf dashboard for tracking and publishing
• Debug RTL failures (waveform/Verdi) and provide actionable feedback to the design team/verification team.
• Contribute to automation of verification/regression and power/performance measurement flows (Python).

 
Minimum Qualifications

• Proven System Verilog + UVM verification experience (testbench architecture, sequences, drivers/monitors).
• Functional coverage, constrained-random, and assertion-based verification (SVA); coverage closure.
• Strong RTL debug with industry simulators (VCS / Xcelium / Questa) and waveform tools (Verdi).
• Working knowledge of RTL design principles and digital design fundamentals.
• Proficiency in Python (or Perl) scripting for automation.

 
Preferred Qualifications

• Experience with power measurement tools Primetime PX (PTPX) or equivalent (e.g., Prime Power).
• Low-power / power-aware verification (UPF, power-aware sim) in advanced nodes (7nm and below).
• Formal verification and/or emulation (Palladium / Zebu) experience.
• Familiarity with the RTL-to-GDSII flow.
• Data analysis / ML approaches for coverage or debug triage.
• Previous experience preferred.

 
Education:

• BS in Electrical/Computer Engineering or Computer Science required; MS preferred (not required).

 
Must Have Skills

• System Verilog / UVM testbench development.
• Functional coverage + assertion-based verification and coverage closure.
• RTL debug (VCS/Xcelsius) + Python automation; power/perf measurement.

 
Pay Transparency: The typical base pay for this role across the U.S. is: $82.00 - $85.00 /hour. Non-exempt positions are eligible for overtime at a rate of 1.5 times the base hourly rate for all hours worked in excess of 40 in a work week, or as required by state or local law. Final offer amounts, within the base pay set forth above, are determined by factors including your relevant skills, education and experience. Full-time employees are eligible to select from different benefits packages. Packages may include medical, dental, and vision benefits, health savings accounts with qualified medical plan enrollment, 10 paid days off, 3 days paid bereavement leave, 401(k) plan participation with employer match, life and disability insurance, commuter benefits, dependent care flexible spending account, accident insurance, critical illness insurance, hospital indemnity insurance, accommodations and reimbursement for work travel, and discretionary performance or recognition bonus. Sick leave and mobile phone reimbursement provided based on state or local law. 
 
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