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FPGA/ASIC Design & Analysis Engineer Level 5
- Location: El Segundo, California 90245
- Employment type: C2C
- Work model: On-site
- Posted August 13, 2026
- Job ID: JPC - 207798
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Job Description
Indotronix is seeking an :
Onsite Job: FPGA/ASIC Design & Analysis Engineer Level 5
Work Location: El Segundo, CA
Shift: First, 8:00 AM to 4:30 PM
Possible OT opportunities
Active Secret Clearance required to start
Required Skills:
- • 5+ years of FPGA and/or ASIC design experience;
- • strong Xilinx/AMD Vivado experience;
- • Experience with Versal family devices;
- • Verilog/SystemVerilog HDL proficiency required;
- • Advanced FPGA implementation skills (synthesis, timing closure, constraints);
- • Active U.S. security clearance
Preferred Skills:
- • 2+ years of FPGA design experience;
- • strong Xilinx/AMD Vivado experience;
- • Verilog/SystemVerilog proficiency;
- • Advanced FPGA implementation skills (synthesis, timing closure, constraints);
General Recruiting Guidance:
- • Demonstrate strong digital hardware fundamentals.
- • Exercise sound engineering judgment.
- • Work independently with minimal oversight.
- • Communicate clearly and proactively.
- • Produce high-quality technical documentation.
- • Take ownership of their work and deliver maintainable engineering solutions.
- • Recruiters should prioritize candidates who can clearly explain their personal technical contributions, design decisions, debugging approach, and ownership of deliverables, rather than simply listing tools or technologies used on a project.
Education / Experience:
- Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
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Job details
Job ID JPC - 207798
Location El Segundo, California, United States
Work Model On-site
Employment Type C2C
Experience 9-14 years
Pay Rate $96.72 - $121.15 (Hourly)
Posted August 13, 2026
Skills AMD Vivado ASIC design FPGA UltraScale Xilinx Xilinx Versal
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