DFT Engineer (Design for Test) Plugins IncDFT Engineer (Design for Test)Santa Clara, CA$70,000–$90,000 / yearContractorFull timeIn this role, you will be responsible for designing and implementing Design-for-Test (DFT) solutions that ensure high manufacturing quality, test coverage, and efficient production testing for complex semiconductor devices. We are seeking an experienced DFT Engineer to join a high-performing ASIC/SoC engineering team.
Physical Design Engineer Einfochips (An Arrow electronics company)Physical Design EngineerSan Jose, CA$110,000–$130,000 / yearContractorFull timeContribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Staff ASIC Design Engineer Celero CommunicationsStaff ASIC Design EngineerSan Jose, CaliforniaCelero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to the development of optical transceivers for next-generation optical modems. Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.) .
ASIC Design Engineer Hewlett Packard Enterprise CompanyASIC Design EngineerSunnyvale, CAFull timeAccountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
Sr. ASIC Design Engineer Starshield Space Exploration Technologies CorpSr. ASIC Design Engineer StarshieldHawthorne, CA$160,000–$225,000 / yearYou will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Principal ASIC Design Engineer Starshield Space Exploration Technologies CorpPrincipal ASIC Design Engineer StarshieldHawthorne, CA$200,000–$285,000 / yearYou will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace. ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Senior ASIC Design Engineer Zp Group LlcSenior ASIC Design EngineerSaratoga, CA$250,000–$290,000 / yearKeywords: ASIC, ASIC Architect, Networking ASIC, AI Networking, Design, Microarchitecture, Performance Modeling, PCIe, SerDes, Ethernet, TCP/IP, RoCE, High-Speed Datapath, Silicon Validation, System-on-Chip, SoC Architecture, Hardware Design, IP Integration, Physical Design, Firmware Interface, Chip Architect, DPU, CPU, SOC. Qualifications for Senior ASIC Design Engineer: 10+ years of experience as an Chip Architect, preferably in networking or high-performance computing (Routers, Switches, GPU, CPU, Data Center, etc).
ASIC Design Engineer lll Hewlett Packard EnterpriseASIC Design Engineer lllSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. The successful candidate will be responsible for the microarchitecture, RTL implementation, integration, and bring-up of high-performance networking IPs and subsystems used in next-generation switch, router, SmartNIC, DPU, and AI networking products.
Digital ASIC Design Engineer for Mixed-Signal IPs Qualcomm IncDigital ASIC Design Engineer for Mixed-Signal IPsSan Diego, CA$115,600–$173,400 / yearGeneral Summary: The Mixed-Signal IP team at Qualcomm is seeking skilled RTL and ASIC design engineers to contribute to the development of next-generation Mixed-Signal IPs - including DAC, ADC, and PLLs - for integration across Qualcomm's product portfolio. 2+ years of hands-on experience in RTL design and ASIC implementation of mixed-signal IPs such as SerDes DDR PHY, PLLs, DACs, ADCs, and sensors.
ASIC/SoC Design Engineer, RTL design for SoC IPs Advanced Micro Devices IncASIC/SoC Design Engineer, RTL design for SoC IPsSan Jose, CAKnowledge of ARM architecture and AMBA protocol specifications Familiarity with PCIe or CXL transaction layer protocols Experience with low-power design techniques (clock gating, power gating, voltage scaling) Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting Exposure to formal verification tools for equivalence checking and property verification Familiarity with AI-assisted design tools and modern EDA technologies Experience mentoring junior engineers and leading design teams Strong technical writing skills for design specifications and documentation Excellent communication and collaboration skills in cross-functional environments. RTL Design & Microarchitecture: • Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
ASIC Design Engineer lll Hewlett Packard Enterprise CoASIC Design Engineer lllSunnyvale, CA$120,000–$243,000 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
Principal Digital Design Engineer - ASIC and FPGA GreenWave RadiosPrincipal Digital Design Engineer - ASIC and FPGAIrvine, CA$190,000–$225,000 / yearOur cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. You'll own everything from architecture through production—defining features, authoring device specifications, and driving the design flow for high-performance programmable logic with embedded Linux-based wireless communications software.
ASIC Design Engineer (Video Silicon IP) - Multimedia Lab Beijing ByteDance Technology Co LtdASIC Design Engineer (Video Silicon IP) - Multimedia LabSan Jose, CAThe successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. Team Introduction The Video Silicon IP team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users.
Sr. ASIC Design Engineer (Video Silicon IP) - Multimedia Lab Beijing ByteDance Technology Co LtdSr. ASIC Design Engineer (Video Silicon IP) - Multimedia LabSan Jose, CAThe successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. Design and implement RTL (SystemVerilog/Verilog) for video codec pipeline stages including intra/inter prediction, transform & quantization, entropy coding (CABAC/ANS), in-loop filters, and etc.
Sr. Engineer, ASIC Design Ayar LabsSr. Engineer, ASIC DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
Principal ASIC Design Engineer Hewlett Packard Enterprise CoPrincipal ASIC Design EngineerSunnyvale, CA$174,000–$352,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
Principal ASIC Design Engineer Hewlett Packard EnterprisePrincipal ASIC Design EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Determines architecture and logic design, design verification through software developed for component and system simulation and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.
ASIC Design Engineer Hewlett Packard EnterpriseASIC Design EngineerSunnyvale, CaliforniaAccountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more} What We Can Offer You: Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
ASIC Design Engineer (eInfochips) Arrow Electronics IncASIC Design Engineer (eInfochips)Mountain View, CAAlong with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.
ASIC Design Engineer - Neural Engine DMA Apple IncASIC Design Engineer - Neural Engine DMASunnyvale, CAWorking closely with design verification and formal verification teams to ensure functional correctness: reviewing test plans, debugging failures, and ensuring the designs intended behavior is fully exercised. In this front-end design role, your work will include: Writing well-parameterized RTL structured for correct synthesis, clean timing, and low power, along with assertions and cover points that encode design intent and ensure verification completeness.
Sr. ASIC Design Engineer Hewlett Packard EnterpriseSr. ASIC Design EngineerRoseville, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
Sr. ASIC Design Engineer Hewlett Packard Enterprise CoSr. ASIC Design EngineerRoseville, CA$153,500–$310,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
Sr. Engineer, ASIC Design Ayar Labs IncSr. Engineer, ASIC DesignSan Jose, CA$160,000–$192,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
SR ASIC SoC Design Engineer Advanced Micro Devices IncSR ASIC SoC Design EngineerSanta Clara, CAWe are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production. THE TEAM: Our group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generation AI networking workloads.
Cellular ASIC Design Engineer - Protocols Apple IncCellular ASIC Design Engineer - ProtocolsCAYou will own the full lifecycle from early architectural exploration and HW/SW partitioning, through RTL implementation, to silicon bring-up and lab validation. Were looking for a Cellular ASIC Design Engineer, where you will architect and implement protocol processing hardware for next-generation wireless SoCs.
ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration Amazon.com IncASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning AccelerationCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
ASIC Design Engineer Qualcomm IncASIC Design EngineerSanta Clara, CA$126,700–$190,100 / yearQCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. Required Skill: 5+ years of industry experience in ASIC design, micro-architecture, and design integration, Strong background in SoC micro-architecture, including specification, definition, and implementation of functional blocks.
Sr. ASIC Design Engineer MicronSr. ASIC Design EngineerSan Jose, CaliforniaAs a Senior ASIC Design Engineer and domain expert, you will perform logic design across the full ASIC lifecycle from specifications and microarchitecture to design, integration, synthesis, timing, linting, and CDC. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O Advanced Micro Devices IncSR ASIC Design Engineer - Ethernet Switch & High-Speed I/OSanta Clara, CAAs a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
SR ASIC Design Engineer - NoC & AXI Interconnect Advanced Micro Devices, IncSR ASIC Design Engineer - NoC & AXI InterconnectSanta Clara, CaliforniaAs a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs Amazon.com IncASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna LabsCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. Collaborate closely with cross-functional teams, including architects, fellow designers, verification specialists, pre- and post-silicon validation teams, and synthesis, timing, and back-end experts.
ASIC Design Verification Engineer (Hardware Security) Qualcomm IncASIC Design Verification Engineer (Hardware Security)Santa Clara, CA$153,200–$229,800 / yearThe Hardware Security team works on cutting edge security solution products for premium Snapdragon chip sets and is seeking Hardware Design engineers with solid ASIC design experience in San Diego, CA. The work will expose the candidate to all aspects of hardware security product creation flow, including Architecture, Microarchitecture, Design, Validation, IP development, Synthesis, Timing closure, Layout, and thorough Silicon Testing.
Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer Qualcomm IncNext-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design EngineerSan Diego, CA$140,000–$210,000 / yearNext Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for a Senior ASIC Design Engineers for the next generation high speed HBM/LPDDR/DDR memory subsystems. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high speed (1Ghz+) designs in QCT products.
Sr. Staff Engineer, ASIC Design Ayar LabsSr. Staff Engineer, ASIC DesignSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
ASIC Design Verification Engineer Waymo LLCASIC Design Verification EngineerMountain View, CA$175,000–$215,000 / yearSince its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World''s Most Experienced Driver-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states.
Sr. Staff ASIC Design Verification Engineer RivianSr. Staff ASIC Design Verification EngineerPalo Alto, California$237,000–$296,000 / yearFull timeRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services.
ASIC Design Engineer Apple IncASIC Design EngineerSanta Clara, CAKnowledge of high-performance memory subsystem, including dram controller, PHY architecture and design, DFI interface and dram interface calibration/training mechanisms and algorithms is a plus. As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day.
Senior ASIC Design Engineer Ethan Alexander GroupSenior ASIC Design EngineerSan Francisco, CaliforniaFamiliarity with lab equipment including logic analyzers, oscilloscopes, and multimeters. Define and bring up FPGA platforms for pre-silicon validation and software development.
ASIC Design Engineer (All Levels) 31 MSIASIC Design Engineer (All Levels)CaliforniaExperience in micro-architecture of complex custom/ASIC products, focusing in one or more of the following areas: NPU, embedded processors, DSP, graphics, and general-purpose microprocessors. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
ASIC Design Engineer - Pixel IP DMA Apple IncASIC Design Engineer - Pixel IP DMACupertino, CAWorking with design verification and formal verification teams to verify functionality and performanceBachelors Degree + 3 years of experienceExperience in multimedia IP/SoC front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal communication skills Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks. As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
Front-End ASIC Design Engineer - [FullTime] (IK) Central Business SolutionsFront-End ASIC Design Engineer - [FullTime] (IK)Milpitas, CaliforniaSkills Required – Micro-architecture at module/sub-system/chip-level; digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings; integration of IPs/modules/sub-systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC execution and analysis; writing timing constraints and timing analysis; excellent debug skills; customer support. Experience and domain-knowledge in at least 2-3 of these: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC/Fabric; low-power design and verification; high-speed peripheral interfaces such as CSI, HDMI/DP, I3C, USB, PCIe; Machine-learning / AI; FPGA.
NewSenior ASIC/SoC RTL Design Engineer: IP & Tape-Out Lead AMDSenior ASIC/SoC RTL Design Engineer: IP & Tape-Out LeadSan Jose, CAA leading semiconductor company in San Jose is seeking a Senior ASIC Design Engineer to design and develop cutting-edge IPs for embedded products. The ideal candidate has expertise in Verilog coding and a robust understanding of the ASIC design flow, with multiple tape-outs.
ASIC Design Engineer - Cache Controller Apple IncASIC Design Engineer - Cache ControllerSanta Clara, CAWork with physical design team on the timing closure of the cache subsystem.10 + years of full time ASIC design experience memory system development RTL/micro-architecture definition PPA (performance/power/area) analysis Cache design background including an understanding of different memory organizations and tradeoffs. Hands on Experience with multi-processor cache coherence protocols B.S. in a relevant fieldKnowledge of high-performance coherent memory systems or interconnect architectures Knowledge of high-performance DRAM controller M.S in a relevant field.
ASIC Design Engineer Marvell Technology IncASIC Design EngineerCAStrong background in high-performance DSP and high-speed datapath design, including pipelined arithmetic units, algorithm-driven hardware implementation, packet processing engines, memory subsystems, and large-scale control/state machines. • Drive post-silicon bring-up and debug, collaborating with lab and systems teams to validate functionality, characterize performance, and resolve complex issues across datapath, DSP, and protocol layers.
NewSenior Physical Design Engineer, ASIC Tapeouts einfochipsSenior Physical Design Engineer, ASIC TapeoutsSan Jose, CAYou will engage in advanced ASIC design activities, integrating high-speed interfaces and managing comprehensive signoff processes while providing technical mentorship. A leading global technology provider in San Jose seeks a mid-senior level Sr.
ASIC Design Engineer I, Satellite Communications Amazon.com IncASIC Design Engineer I, Satellite CommunicationsSan Diego, CAThe team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. Amazon Leo is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.
ASIC Design Engineer Hewlett Packard Enterprise CoASIC Design EngineerSunnyvale, CA$120,000–$243,000 / yearAdditional Skills: Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs Amazon.com IncSr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna LabsCupertino, CAAs a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server. We pioneered cloud computing and never stopped innovating - that's why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.
Sr. Staff Engineer, ASIC Design Ayar Labs IncSr. Staff Engineer, ASIC DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD, and Intel, and manufactured in partnership with the worlds leading semiconductor ecosystem, Ayar Labs co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. • Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation, clocks, and timing constraints, floorplan guidance, testability, and collaborate to ensure timing signoff.
Senior ASIC Design Engineer - Hardware NVIDIASenior ASIC Design Engineer - HardwareUs, CaliforniaThis position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.