Junior/New Graduate ASIC Design Engineer - Machine Learning (ML) Accelerator

About EdgeQ

EdgeQ is a leading innovator developing the industry's first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 1-5 Years, or new Graduate

Location: Santa Clara, US

Responsibilities

• Design and implement digital logic blocks for ML accelerator subsystems using SystemVerilog
• Develop RTL for control logic, arithmetic datapaths, register interfaces, FIFOs, and bus/DMA interfaces according to specifications
• Work with the design and verification teams to simulate and debug blocks, and close functional coverage
• Run front-end checks (Lint, CDC, synthesis) and help optimize designs for area, timing, and power
• Help build C/Python reference models and test vectors with the architecture and software teams
• Develop scripts and tools to automate design and verification flows
• Support FPGA prototyping, block integration, and post-silicon validation and benchmarking
• Learn ML accelerator architecture and workload mapping under the mentorship of senior engineers

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field, with 1-5 years of experience; new graduates (MS/PhD) are welcome
• Excellent knowledge of digital logic design: combinational/sequential logic, FSMs, pipelining, timing (setup/hold), and arithmetic circuits
• Excellent knowledge of computer architecture and microprocessors: instruction pipelines, hazards, caches, memory hierarchy, and interrupts
• Hands-on RTL design experience in Verilog/SystemVerilog through projects, internships, or industry work
• Coursework or project experience in machine learning and neural network fundamentals
• Experience designing a processor (e.g. RISC-V core), systolic array, or ML accelerator in coursework, research, or FPGA projects is a strong plus
• Familiarity with simulation and synthesis tools (e.g. VCS/Xcelium, Verdi, Design Compiler/Genus, Vivado/Quartus)
• Understanding of integer/floating-point arithmetic, clock domain crossing, and low-power design concepts is a plus
• Programming/scripting skills in C/C++ and Python; familiarity with PyTorch or TensorFlow is a plus
• Strong problem-solving skills, eagerness to learn, and good communication and teamwork skills