Intel in California seeks an experienced verification engineer to architect and verify silicon designs, define verification strategy, and develop reusable testbenches. You will integrate block testbenches into chip‑level UVM environments, run functional simulations, and collaborate with analog and digital teams to ensure specification conformance.Strong skills in SystemVerilog, C/C++/Python, hardware simulation tools, OVM/UVM, and a track record of closure on coverage goals are required.#J-18808-Ljbffr
| Location | Folsom, CA |