Senior Staff ASIC Design Engineer - Machine Learning (ML) Accelerator

About EdgeQ

EdgeQ is a leading innovator developing the industry's first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 10+ Years

Location: Santa Clara, US

Responsibilities

• Define the overall HW architecture of the ML accelerator, including compute engines, memory hierarchy, interconnect, and control
• Translate target workloads and system requirements into architecture and micro-architecture specifications with clear PPA (TOPS/W, TOPS/mm²) targets
• Perform workload analysis and architecture exploration (roofline, utilization, bandwidth, latency) to size compute and memory resources
• Drive HW/SW co-design with the compiler, runtime, and firmware teams, including ISA and programming model definition
• Architect power and area efficient MAC arrays, vector units, activation/normalization units, and data-movement engines
• Lead block-level and subsystem-level RTL design teams; review micro-architecture, RTL, and verification plans
• Own PPA closure of the accelerator together with physical design, ensuring timing, area, and power goals are met
• Collaborate with modem architecture, SoC integration, verification, DFT, and physical design teams
• Support post-silicon bring-up, debug, and performance benchmarking
• Mentor staff and junior engineers and set design methodology and quality standards

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field with 10+ years of ASIC design experience
• Proven track record of architecting and taping out ML/AI accelerators, GPUs, DSPs, or high-performance compute engines
• Deep understanding of ML/AI accelerator architecture: matrix/tensor engines, systolic arrays, dataflow (weight/output/row stationary), and vector/SIMD units
• Expert in power, performance and area (PPA) trade-offs: roofline analysis, data reuse, clock and power gating, DVFS, and low-power design (UPF)
• Expert in SystemVerilog RTL and front-end flows (Lint, CDC/RDC, LEC, synthesis, STA constraints, power analysis)
• Experience with RISC-V or custom ISA extensions for ML, and HW/SW co-design with ML compilers and runtimes (e.g. TVM, MLIR, ONNX)
• Strong knowledge of neural network workloads (CNN, RNN, Transformer/attention, LLM inference) and their compute, memory, and bandwidth characteristics
• Experience with numeric formats and quantization (INT8/INT4, FP16/BF16/FP8, block floating point) and sparsity/compression techniques
• Expert in on-chip memory hierarchy design: SRAM banking, scratchpads, DMA engines, prefetch, and DDR/LPDDR bandwidth optimization
• Familiarity with ML workloads for wireless (AI-native PHY, channel estimation, beam management) is a plus
• Excellent written and verbal communication; able to lead cross-functional technical discussions and mentor engineers