Staff ASIC Design Engineer - 4G/5G/6G Modem

About EdgeQ

EdgeQ is a leading innovator developing the industry's first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 5+ Years

Location: Santa Clara, US

Responsibilities

• Design the micro-architecture of modem sub-blocks based on system-level architecture specifications
• Implement power and area efficient sub-blocks with SystemVerilog, e.g. channel estimation, MIMO equalizer, FFT, LDPC/Polar decoder, and NTN Doppler/timing compensation
• Write micro-architecture specifications and design documents
• Develop control and datapath RTL, run Lint/CDC/LEC, and integrate sub-blocks into subsystems
• Perform bit-exact verification against C/MATLAB reference models with the algorithm team
• Optimize the HW to meet area, timing, and power targets; perform synthesis and power analysis
• Implement low-power logic (clock gating, power domains, memory power management)
• Work with the Design Verification team on block-level and top-level functional/gate-level verification and coverage, including power-aware debug
• Support physical design for timing closure and post-silicon bring-up and debug
• Guide and review the work of junior engineers

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field with 5+ years of ASIC design experience
• Professional knowledge and experience in SystemVerilog RTL design
• Professional knowledge of digital signal processing and wireless communication; familiarity with 4G LTE / 5G NR physical layer
• Experience designing DSP datapaths such as FFT, filters, correlators, MMSE/ML equalizers, matrix operations, or LDPC/Polar encoders/decoders
• Strong skills in fixed-point arithmetic, pipelining, and resource sharing for area and power optimization
• Hands-on experience in front-end chip development: Lint, CDC, LEC, synthesis, timing constraints, and low-power checks (UPF)
• Experience with multiple clock domains and asynchronous interfaces
• Experience writing micro-architecture specifications and converting them to design
• Knowledge of on-chip buses (AXI/AHB/APB), SRAM interfaces, and memory banking
• Knowledge of 5G NTN (satellite) features such as Doppler and timing compensation is a plus
• Ability to communicate effectively across all internal groups