Staff ASIC Design Engineer - Machine Learning (ML) Accelerator

About EdgeQ

EdgeQ is a leading innovator developing the industry's first 5G/6G base station on a chip for terrestrial and non-terrestrial network (NTN) markets. Recognized with multiple Global Mobile (GLOMO) Awards at Mobile World Congress Barcelona 2023, EdgeQ is led by seasoned executives from Qualcomm, Intel, and Broadcom who have delivered industry-transforming technologies spanning 4G, 5G, Wi-Fi, WiMAX, artificial intelligence, and cloud servers. EdgeQ is creating a new paradigm for wireless infrastructure: a flexible, cloud-based platform designed to extend robust internet access and communications to remote and densely populated areas and support the next trillion connected devices.

Experience: 5+ Years

Location: Santa Clara, US

Responsibilities

• Design the micro-architecture of ML accelerator sub-blocks based on system-level architecture specifications
• Implement power and area efficient sub-blocks with SystemVerilog, e.g. MAC arrays, vector engines, activation/normalization units, data-movement and memory controllers
• Write micro-architecture specifications and design documents
• Develop control and datapath RTL, run Lint/CDC/LEC, and integrate sub-blocks into the accelerator subsystem
• Perform bit-exact verification against C/C++/Python reference models with the architecture and software teams
• Optimize the HW to meet area, timing, and power targets; perform synthesis and power analysis
• Implement low-power logic (clock gating, power domains, memory power management)
• Work with the Design Verification team on block-level and top-level functional/gate-level verification and coverage, including power-aware debug
• Support physical design for timing closure and post-silicon bring-up, debug, and performance measurement
• Guide and review the work of junior engineers

Job Requirements

• BS/MS/PhD in Electrical/Computer Engineering or related field with 5+ years of ASIC design experience
• Professional knowledge and experience in System Verilog RTL design
• Experience designing ML accelerator or compute building blocks such as MAC/systolic arrays, vector/SIMD units, activation/pooling/normalization units, or DMA engines
• Solid understanding of neural network operations (convolution, GEMM, attention, softmax) and their mapping to hardware
• Knowledge of numeric formats and quantization (INT8/INT4, FP16/BF16/FP8) and floating-point/fixed-point arithmetic design
• Strong skills in pipelining, data reuse, and resource sharing for area and power optimization
• Hands-on experience in front-end chip development: Lint, CDC, LEC, synthesis, timing constraints, and low-power checks (UPF)
• Experience with multiple clock domains and asynchronous interfaces
• Experience writing micro-architecture specifications and converting them to design
• Knowledge of on-chip buses (AXI/AHB/APB), SRAM interfaces, memory banking, and scratchpad design
• Ability to communicate effectively across all internal groups