High-quality, high-performance Verilog/SystemVerilog RTL implementation based on a design specification - may also include areas such as asynchronous clock domain crossings, multiple power domains, low-power design, complex algorithms, deep computations and pipelining, multi-threaded designs, and integrating third-party IP. Working with cross functional teams such as Verification Engineering, Software/Firmware Engineering, Emulation Engineering, and Validation Engineering to support any issues that may arise on the RTL design.