Principal Design Engineer DustPhotonics LtdPrincipal Design EngineerSan Jose, CA$180,000–$250,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. In this role, you will be responsible for the RTL architecture, design, implementation, and verification of advanced SerDes PHY Digital Signal Processing (DSP) blocks used in next-generation networking, AI, data center, and high-performance computing products.
SerDes RTL Design Engineer Advanced Micro Devices IncSerDes RTL Design EngineerSan Jose, CATHE ROLE: AMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
PLL Design/ Integration Staff Engineer - Adaptive Computing Group Advanced Micro Devices IncPLL Design/ Integration Staff Engineer - Adaptive Computing GroupSan Jose, CAKEY RESPONSIBILITIES: Architect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider in to FPGA products across cutting-edge process nodes. Our team collaborates closely with functional architecture, programmable fabric, integration, and software teams to design and deliver innovative clocking solutions - spanning new architectures, clock IPs, tools, and flows.
RTL Design & Integration Engineer Advanced Micro Devices IncRTL Design & Integration EngineerSan Jose, CAYou will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting PPA, cost and schedule optimized Silicon implementation and first-time-right SW solution. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward.
Design Staff Atelier TenDesign StaffSan Francisco, CaliforniaWe’re an innovative multidisciplinary firm of environmental design consultants, building services engineers and lighting designers focused on delivering high-quality, award-winning building services and sustainable design within the built environment sector. Collaborate Atelier Ten’s integrated design groups to support the full range of our services, which include environmental design consulting, daylight and façade analysis, carbon analysis design and benchmarking.
RTL Design Engineer, TPU and ML Google LLCRTL Design Engineer, TPU and MLSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. In this role, you will join the team designing and developing the On-Chip Network of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters.
Senior Design and Integration Engineer, Cloud TPU Google LLCSenior Design and Integration Engineer, Cloud TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Join the team designing and developing the On-Chip Network of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters.
TPU Hardware Design Engineer, Cloud Google LLCTPU Hardware Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You will join the team designing and developing the on-chip network of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
Creative Director, Design Meta Platforms IncCreative Director, DesignBurlingame, CAYou will partner with product designers, content designers, industrial designers, motion designers, creative technologists, and engineers to ship high-quality digital retail experiences for our expanding hardware portfolio. We have developed best-in-class collaboration models with agencies and our cross-company creative network to ensure a consistent and effective creative narrative for work that reaches an audience across the globe due to the scale of our products.
Staff ASIC Design Verification Engineer Google LLCStaff ASIC Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Were the driving force behind Googles groundbreaking innovations empowering the development of our cutting-edge AI models delivering unparalleled computing power to global services and providing the essential platforms that enable developers to build the future.
Senior Design Engineer (MOSFET / IGBT) Alpha & Omega SemiconductorSenior Design Engineer (MOSFET / IGBT)Sunnyvale, CAFull timeAt Alpha and Omega Semiconductor (AOS), we design, develop and globally supply a broad range of power semiconductors, including a wide portfolio of Power MOSFET, IGBT, IPM, TVS, GaN/SiC, Power IC and Digital Power products. Primary job functions include:Power device structure and process simulation with TCAD tools including Tsuprem4, Medici, and SentaurusDevice characterization with LCR meter, curve tracer, FET test, etc.
Senior Design Verification Engineer AuradineSenior Design Verification EngineerSanta Clara, CA$200,000–$500,000 / yearYou will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. You will help establish confidence in the correctness, performance, reliability, and safety of the architecture-from individual RTL blocks to complete HW/SW systems running real-world workloads.
Silicon Design Verification Engineer Advanced Micro Devices IncSilicon Design Verification EngineerSan Jose, CAYou will plan, develop, and execute comprehensive verification strategies across complex digital subsystems, working closely with cross-functional engineering teams to deliver robust, bug-free designs. You bring strong analytical and debugging skills, communicate effectively across globally distributed teams, and are motivated to learn new technologies while taking ownership of difficult problems.
FPGA Design Engineer (MTD, Tualatin, OR) Teradyne IncFPGA Design Engineer (MTD, Tualatin, OR)San Jose, CA$123,100–$196,900 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Senior FPGA Design Engineer (MTD, Tualatin, OR) Teradyne IncSenior FPGA Design Engineer (MTD, Tualatin, OR)San Jose, CA$154,900–$247,800 / yearOur test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.
Sr Principal Design Engineer Cadence Design Systems IncSr Principal Design EngineerSan Jose, CA$154,000–$286,000 / yearYou will bridge the gap between customers, Applications Engineering (AE), Product Engineering (PE), and R&D - develop impactful customer solutions, delivering deep R&D technical support, and pioneering innovative verification methodologies to solve our customers' most complex architectural and high-Speed Protocol challenges. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence's market-leading hardware emulation and FPGA prototyping platforms.
CPU Core Design Verification Testbench Lead Tenstorrent IncCPU Core Design Verification Testbench LeadSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. How Tenstorrent applies AI across the DV lifecycle - from test planning and stimulus through regression debug, triage, and coverage analysis - using workflows designed to keep context tight and outputs auditable.
NewCPU Core Design Verification Testbench Lead TenstorrentCPU Core Design Verification Testbench LeadSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. How Tenstorrent applies AI across the DV lifecycle - from test planning and stimulus through regression debug, triage, and coverage analysis - using workflows designed to keep context tight and outputs auditable.
SoC Design Engineer OmnivisionSoC Design EngineerSanta Clara, California$110,600–$140,000 / yearFamiliar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
Standard Cell Design Lead SubstrateStandard Cell Design LeadSan Francisco, CaliforniaThis role requires deep expertise in digital cell design, layout, and timing characterization combined with strong understanding of library requirements for digital design flows. At the intersection of advanced manufacturing and cutting-edge physics, we are developing technologies that will reshape the semiconductor industry and strengthen America's technological leadership.