8,050 Results for

Administration Jobs in Oconomowoc, WI

Jobs

Senior Architecture Project Manager - Science HDR Inc

San Francisco, CA

$156,156–$223,080 / year

States-California-San Francisco'',''United States-California-San Francisco'','''','''','''','''','''','''','''','''',''Architecture'',''Architecture'',''Full-time'',''Full-time'',''Regular'',''Regular'','''','''',''EdSciSport ARC'',''EdSciSport ARC'',''Jun 4, 2026'',''Jun 4, 2026'',''false'',''785056'',''785056'',''true'',''785056'',''false'',''Submission for the position: Senior Architecture Project Manager - Science - (Job Number: 193615)'',''false'',''785056'',''false'',''true''. '',''We provide a comprehensive benefits package that promotes employee ownership, employee health, performance, and success, which includes medical, dental, vision, short and long-term disability, life insurance, an employee assistance program, paid time away, parental leave, paid holidays, a retirement savings plan with employer match, employee referral bonus and tuition reimbursement.

30+ days ago

Architecture Project Manager - Science HDR Inc

San Francisco, CA

$145,145–$207,350 / year

States-California-San Francisco'',''United States-California-San Francisco'',''United States-California-Folsom'',''United States-California-Folsom'','''','''','''','''','''','''',''Architecture'',''Architecture'',''Full-time'',''Full-time'',''Regular'',''Regular'','''','''',''EdSciSport ARC'',''EdSciSport ARC'',''Jun 5, 2026'',''Jun 5, 2026'',''false'',''785055'',''785055'',''true'',''785055'',''false'',''Submission for the position: Architecture Project Manager - Science - (Job Number: 193613)'',''false'',''785055'',''false'',''true''. '',''We provide a comprehensive benefits package that promotes employee ownership, employee health, performance, and success, which includes medical, dental, vision, short and long-term disability, life insurance, an employee assistance program, paid time away, parental leave, paid holidays, a retirement savings plan with employer match, employee referral bonus and tuition reimbursement.

30+ days ago

Senior Manager, Technical Architecture Okta Inc

San Francisco, CA

Remote

Classification of protected categories is as follows: A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability. The annual OTE range for this position for candidates located in California (excluding San Francisco Bay Area), Colorado, Illinois, New York, and Washington is between:$208,000-$286,000 USDThe Okta Experience Supporting Your Well-Being Driving Social Impact Developing Talent and Fostering Connection + Community We are intentional about connection.

30+ days ago

Senior Project Manager (Healthcare Architecture) HDR Inc

San Francisco, CA

$156,156–$223,080 / year

States-California-San Francisco'',''United States-California-San Francisco'',''United States-California-Folsom'',''United States-California-Folsom'','''','''','''','''','''','''',''Architecture'',''Architecture'',''Full-time'',''Full-time'',''Regular'',''Regular'','''','''',''Health ARC'',''Health ARC'',''Aug 25, 2026'',''Aug 25, 2026'',''false'',''790401'',''790401'',''true'',''790401'',''false'',''Submission for the position: Senior Project Manager (Healthcare Architecture) - (Job Number: 195659)'',''false'',''790401'',''false'',''true''. '',''We provide a comprehensive benefits package that promotes employee ownership, employee health, performance, and success, which includes medical, dental, vision, short and long-term disability, life insurance, an employee assistance program, paid time away, parental leave, paid holidays, a retirement savings plan with employer match, employee referral bonus and tuition reimbursement.

30+ days ago

Engineering Manager - Architecture Efficient Computer

San Francisco, Pennsylvania

$200,000–$260,000 / year

Our Fabric architecture delivers a 10–100x improvement in energy efficiency for general-purpose computation, including AI, while supporting familiar programming languages and software frameworks—unlocking new possibilities for autonomous machines, intelligent infrastructure, wearables, and space systems. Planning and tracking the work of the architecture team, including: Working closely with technical leads to prioritize work and set roadmaps based on business requirements from the Product, Sales and Marketing teams.

6 days ago

ASIC Engineer, Architecture Meta Platforms Inc

Sunnyvale, CA

Degree must be completed prior to joining Meta Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in ASIC design, silicon engineering, or a related technical field Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs Experience with the performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon Experience developing cycle-accurate or transaction-level performance models using C++ and SystemC for complex digital systems, including processors, memory subsystems, or high-speed interconnects Experience defining microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams Experience with assembly programming languages, and with compiler technologies Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience writing and optimizing compute/collective kernels in CUDA or equivalent GPU programming frameworks Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies Experience with AI numerics, data types, math functions, and precision/accuracy analysis Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flowsMeta builds technologies that help people connect, find communities, and grow businesses. In this role, you will establish functional and performance modeling methodologies and long-term silicon roadmap strategy, as well as develop and analyze workloads, partnering with architecture, design, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.

30+ days ago

Staff / Principal Engineer, Backend Architecture Recruiting From Scratch

San Francisco, California

$130,000–$400,000 / year

Their platform connects leading AI labs and enterprises with a global network of experts who generate the high-quality human intelligence required to train and evaluate frontier AI models. Location: San Francisco, CA Company Stage of Funding: Series C AI Marketplace ($10B Valuation) Office Type: Onsite (5 Days Per Week) Salary: $130,000–$500,000 + Equity.

30+ days ago

SoC Power Architecture Engineer - Processor Subsystem E-Space

Saratoga, CA

$150,000–$220,000 / year
Full time

This role focuses on partitioning and structuring power domains within complex processor subsystems, with a strong emphasis on the aggressive duty cycling, ultra-low standby power, and constrained energy budgets inherent to satellite IoT end-node devices. We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement power domain architectures for ASIC-based processor subsystems targeting satellite IoT connectivity applications.

30+ days ago

Director Of Buffer & Memory Subsystem Architecture SK hynix

San Jose, CA

$250,000–$300,000 / year

Qualifications: 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures, including the development of queueing, scheduling, and buffer management algorithms. Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC, or comparable modeling environments, including event-driven, trace-driven, or queueing-based models.

30+ days ago

Senior Storage AI Specialist Solution Architect , AGS Specialist Solutions Architecture Team Amazon.com Inc

Santa Clara, CA

You will have the technical depth and business experience to deploy storage and data strategies, Act as a thought leader sharing best practices through forums such as AWS blogs, whitepapers, reference architectures and public-speaking events such as AWS Summit, AWS re: Invent, etc. You"ll partner with field Solution Architects to provide guidance on customer engagements, while creating white papers, blogs, reference architectures, and presentations that empower customers to fully utilize AWS capabilities.

4 days ago

CV/ML Systems Engineer, Hardware Architecture Meta Platforms Inc

Burlingame, CA

Drive organization-wide software integration programs onto hardware platforms, orchestrating cross-functional teams across silicon engineering, ML platform, perception algorithms, and hardware systems to deliver CV/ML capabilities on custom silicon Define and own the end-to-end program roadmap for integrating CV/ML inference pipelines onto VR headsets, AR glasses, and wearable spatial computing platforms across multiple product generations Lead hardware-software co-design initiatives by aligning software development milestones with silicon tape-out schedules, ensuring timely integration of perception algorithms onto target hardware Establish integration requirements, success criteria, and program milestones that translate perception algorithm demands into actionable deliverables across hardware and software teams Identify and resolve cross-functional dependencies, risks, and bottlenecks in software-to-hardware integration programs, driving accountability across engineering organizations Coordinate with silicon engineering, firmware, and platform teams to define architectural requirements for custom CV/ML accelerators and SoCs based on software integration needs Develop and maintain program tracking frameworks to evaluate integration progress, hardware readiness, and software maturity against real-world CV/ML workload requirements Engage with external silicon partners, sensor vendors, and IP providers to align integration timelines and ensure emerging CV/ML hardware technologies are incorporated into program plans Communicate program status, integration trade-offs, and roadmap decisions to executive leadership and cross-functional stakeholders through written proposals, program reviews, and status updates Define benchmarking methodologies and integration validation criteria for CV/ML software onto hardware systems across the full stack from sensor ingestion through algorithm execution12+ years of experience in hardware systems architecture with a focus on computer vision, machine learning inference, or high-performance signal processing systems Experience defining SoC or system-level architecture for CV or ML inference workloads, including image signal processor pipelines, compute hierarchy design, memory subsystem architecture, and interconnect topology Experience with hardware-software co-design methodologies for on-device CV/ML workloads, including familiarity with ML compiler stacks, operator fusion, quantization impacts on hardware design, and perception algorithm profiling Experience developing system performance models and using simulation or analytical frameworks to evaluate architectural trade-offs for real-time CV/ML workloads at scale Track record of driving multi-year hardware architecture roadmaps and influencing silicon strategy across large engineering organizations in consumer electronics or spatial computing domains Background in collaborating with computer vision and ML research teams to translate novel perception model architectures into hardware-efficient deployment targets on custom silicon Experience architecting CV/ML inference systems for power- and area-constrained wearable or mobile devices, including VR headsets, AR glasses, or similar spatial computing platforms Experience evaluating and integrating emerging memory and sensor technologies into CV/ML system architectures, including event cameras, time-of-flight sensors, or near-sensor compute approaches Familiarity with perception workloads such as SLAM, depth estimation, hand and eye tracking, scene segmentation, or neural radiance field rendering and their specific hardware demandsMeta builds technologies that help people connect, find communities, and grow businesses. In this role, you will drive end-to-end software integration programs spanning computer vision and machine learning workloads onto custom silicon, sensor subsystems, and hardware platforms powering next-generation virtual and augmented reality products.

17 days ago

Sr. Director, AI Business Architecture & Enterprise Adoption NetApp Inc

San Jose, CA

$227,800–$338,800 / year

This leader will help shape NetApp''s future operating model by leveraging enterprise applications, AI, automation, and digital capabilities to accelerate enterprise transformation, improve business performance, and deliver measurable business outcomes. The role will shape multi-year application strategies, guide portfolio prioritization, influence investment decisions, manage strategic vendor relationships, and lead through directors, managers, employees, contractors, and implementation partners.

16 days ago

Director of Buffer & Memory Subsystem Architecture SK hynix

San Jose, California

8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures, including the development of queueing, scheduling, and buffer management algorithms. Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC, or comparable modeling environments, including event-driven, trace-driven, or queueing-based models.

30+ days ago

Staff Software Engineer, Enterprise Sales Systems Architecture, Google Cloud Business Platform Transact Google LLC

Sunnyvale, CA

Were looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. You will lead the design of highly available, secure, and distributed systems that process high-volume enterprise transactions, ensuring seamless integration between upstream purchasing experiences and downstream billing and fulfillment systems.

12 days ago

Senior Software Engineer, Device Architecture, Google Home Google LLC

Mountain View, CA

Were looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. Formulate architectural blueprints and trade-off analyses to influence internal cross-functional teams (hardware, platform software, Product Management) and external vendor engineering teams.

12 days ago

ASIC Engineer Intern, Architecture Meta Platforms Inc

Sunnyvale, CA

Currently has, or is in the process of obtaining, a Master's Degree in Electrical Engineering, Computer Engineering or related areas Programming skills in C, C++ or related Object Oriented Programming Knowledge of Computer Architecture concepts such as processor architecture, memory systems and on-chip interconnection networks Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment Intent to return to degree-program after the completion of the internship/co-op Currently has, or is in the process of obtaining, a PhD degree in Electrical Engineering, Computer Engineering or related areas Experience in GenAI or machine learning architectures or related experience Experience in developing AI kernels, CUDA programming, parallel programming, C++ code for hardware simulators and exposure to performance and numerical analysis of ASIC designs Creativity and problem solving capabilitiesMeta builds technologies that help people connect, find communities, and grow businesses. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.

2 days ago

Staff Embedded Software Engineer, Pixel System Debug Architecture Google LLC

Mountain View, CA

Were looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. You will bridge hardware, firmware, operating systems, inter-device communication, and cloud analytics to build triage pipelines, resilient reboot/recovery mechanisms, and high-fidelity trace infrastructure while defining stringent PII protection and data governance policies.

20 days ago

Staff Software Engineer, Linux Kernel and Baseboard Management Controller Architecture Google LLC

Sunnyvale, CA

Were looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

3 days ago

Architecture Project Manager: Healthcare LPA

San Jose, California

Opportunities to propose and lead projects that impact your local community, including more than $1 million since 2015 in Habitat for Humanity builds, scholarships, and other pro bono community projects. In the situation an agency or recruiter submits a candidate or resume without a previously signed agreement and/or without LPA’s request , LPA explicitly reserves the right to hire those candidate(s) without any financial obligation to the recruiter or agency.

30+ days ago

Project Manager-Architecture and Engineering AECOM

San Francisco, CA

We invite you to bring your bold ideas and big dreams and become part of a global team of over 50,000 planners, designers, engineers, scientists, digital innovators, program and construction managers and other professionals delivering projects that create a positive and tangible impact around the world. AECOM's Buildings + Places practice is actively seeking a Project Manager to support active and future projects for growing practiceThis position will be located in a hybrid capacity in our San Francisco or Oakland, CA office.

30+ days ago

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Administration Jobs in Oconomowoc, WI

Senior Architecture Project Manager - Science HDR Inc

Architecture Project Manager - Science HDR Inc

Senior Manager, Technical Architecture Okta Inc

Senior Project Manager (Healthcare Architecture) HDR Inc

Engineering Manager - Architecture Efficient Computer

ASIC Engineer, Architecture Meta Platforms Inc

Staff / Principal Engineer, Backend Architecture Recruiting From Scratch

SoC Power Architecture Engineer - Processor Subsystem E-Space

Director Of Buffer & Memory Subsystem Architecture SK hynix

Senior Storage AI Specialist Solution Architect , AGS Specialist Solutions Architecture Team Amazon.com Inc

CV/ML Systems Engineer, Hardware Architecture Meta Platforms Inc

Sr. Director, AI Business Architecture & Enterprise Adoption NetApp Inc

Director of Buffer & Memory Subsystem Architecture SK hynix

Staff Software Engineer, Enterprise Sales Systems Architecture, Google Cloud Business Platform Transact Google LLC

Senior Software Engineer, Device Architecture, Google Home Google LLC

ASIC Engineer Intern, Architecture Meta Platforms Inc

Staff Embedded Software Engineer, Pixel System Debug Architecture Google LLC

Staff Software Engineer, Linux Kernel and Baseboard Management Controller Architecture Google LLC

Architecture Project Manager: Healthcare LPA

Project Manager-Architecture and Engineering AECOM

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