NewArchitectural Designer II - PreK-12 Harley Ellis DevereauxArchitectural Designer II - PreK-12San Francisco, CADesigner is an early career level architecture role that is responsible for assisting project teams with a range of project types from early design through construction under the supervision of a seasoned Architect and/or Project Designer. As a Technical Architectural Designer II, you’ll play a key role in supporting project teams from early design through construction under the guidance of experienced architects and designers.
NewArchitectural Designer IV - PreK-12 Harley Ellis DevereauxArchitectural Designer IV - PreK-12San Francisco, CAJob Description Position Summary: HED is seeking an experienced and passionate Architectural Designer IV to join our growing PreK–12 Education practice in our San Francisco Bay Area, Sacramento, or Los Angeles offices. Project Architect IV is a mid-level technical architecture role that is responsible for leading PreK-12 project scopes from early design through construction under the supervision of a seasoned Architect and/or Project Designer.
NewArchitectural Designer IV - Mission Critical Harley Ellis DevereauxArchitectural Designer IV - Mission CriticalSan Francisco, CAThe ideal candidate will be able to conduct and lead programmatic and design-oriented research, use exceptional graphic skills on competitions, pursuits and project work, and provide renderings (digital modeling and visualization) and physical model building to represent design concepts as a member of one or more project teams. Minimum 10 years' experience in A/E industry preferred, with demonstrated proficiency to lead project design efforts on a range of project sizes and complexity, comfortable leading multiple projects simultaneously when needed.
NewAutoCAD Design/Drafter Auriga CorporationAutoCAD Design/DrafterMilpitas, CAJob Description AURIGA JOB POSTING (Auriga Website: www.aurigacorp.com) Auriga Corporation was established in 1990, to provide high-quality design, engineering and project management services for Electric Power, Telecommunication and Information Technology systems. Proven work experience in preparing computer-aided design of drawings and other graphic material for Electrical, Mechanical, Civil, Structural or Architectural designers using AutoCAD, Map 3D, Civil 3D and/or Revit.
Software Engineer, Agent Architecture SierraSoftware Engineer, Agent ArchitectureSan Francisco, CaliforniaYou’ll build systems that ensure agents provide accurate, trustworthy responses by effectively retrieving and using knowledge. You’ll work on the Agent SDK — the orchestration engine, runtime, and primitives that define how agents reason, take actions, and interact with users and systems.
Principal Engineer, SerDes AMS Design and Architecture Ayar LabsPrincipal Engineer, SerDes AMS Design and ArchitectureSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Key Responsibilities: Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
Designer II, Interior Architecture & Design Ware MalcombDesigner II, Interior Architecture & DesignPleasanton, CAEstablished in 1972, Ware Malcomb is a dynamic, forward-thinking commercial real estate design firm providing professional architecture, interior design, civil engineering, branding, building measurement, structural engineering and MEP engineering services to clients throughout the world. The firm is also ranked among the top 10 Architecture/Engineering firms in Engineering News-Record’s Top 500 Design Firms and the Top 30 Interior Design Firms in Interior Design magazine’s Top 100 Giants.
Sr Staff Engineer Instrument Architecture Becton Dickinson Medical DevicesSr Staff Engineer Instrument ArchitectureMilpitas, CaliforniaWaters collaborates with analytical laboratories around the world to advance the release of effective, high-quality medicines, assure the safety of food and water, and drive better patient outcomes by detecting diseases earlier, managing routine infections, and combatting growing antibiotic resistance. Data Pipeline Architecture: Expert knowledge of high-throughput data processing architectures, including DMA (Direct Memory Access) transfers, FIFO buffering strategies, and high-speed bus interfaces (PCIe, USB 3.0, Gigabit Ethernet).
Fellow, AI Software Architecture Advanced Micro Devices, IncFellow, AI Software ArchitectureSan Jose, CaliforniaAMD AI Group is seeking a highly influential technical leader for the role of AMD Fellow, OneROCm — driving a unified ROCm software stack across AMD’s broad product portfolio, including Instinct, Radeon, Ryzen, Embedded, Game Consoles, and Autonomous Driving platforms. As a s uccessful candidate , y ou are recognized for technical excellence, cross-functional leadership, and the ability to drive company-wide innovation through collaboration across silicon, system software, AI/ML frameworks, libraries, and application enablement teams.
Hardware System Architecture Fellow - AI & Data Center Networking Advanced Micro Devices, IncHardware System Architecture Fellow - AI & Data Center NetworkingSanta Clara, CaliforniaThe Fellow operates with enterprise‑scale technical authority, shaping multi‑generation system architectures and influencing execution across ASIC, packaging, board, optics, power, thermal, mechanical, firmware, and manufacturing domains, without direct people management responsibility. This role provides system‑level technical leadership, spanning architecture definition, cross‑domain trade‑offs, and resolution of the most complex hardware challenges across AI‑NICs, DPUs, switches, and rack‑scale networking solutions.
Fellow - Adaptive SoC / FPGA architecture Advanced Micro Devices, IncFellow - Adaptive SoC / FPGA architectureSan Jose, CaliforniaAs a senior technical leader, you will shape the long‑term vision for bitstream architecture, configuration flows, runtime reconfiguration, debug observability, and system integration, translating customer requirements across Emulation & Prototyping, AI, Data Center, Embedded, and Automotive into differentiated FPGA capabilities. This role will own the architecture for FPGA configuration, readback, and Partial Reconfiguration (PR), enabling scalable, secure, and flexible deployment of programmable logic in heterogeneous SoC and chiplet environments.
Head of System Domain Architecture ASMLHead of System Domain ArchitectureSan Jose, CaliforniaIn this role, you are responsible for ensuring end-to-end domain architectural coherence across relevant products and module generations, while driving the functional roadmap to deliver fit-for-purpose, cost-effective, and maintainable solutions including: Delivering system level domain specific SEG documents and provide input for design rules. Ensures Accountability: The ability to create a clear accountability system where ownership, expectations, and decision rights are explicit; drives consistent follow-through on commitments across teams; and addresses performance or delivery gaps quickly and constructively, while reinforcing a culture of ownership, learning, and measurable outcomes.
Reference Architecture & Content Specialist: 26-01743 Akraya Inc.Reference Architecture & Content Specialist: 26-01743Pleasanton, CARemote$90–$92 / hourMost recently, we were recognized Stevie Employer of the Year 2025, SIA Best Staffing Firm to work for 2025, Inc 5000 Best Workspaces in US (2025 & 2024) and Glassdoor's Best Places to Work (2023 & 2022)! Primary Skills: Diagramming tools (advanced), SIR module knowledge (intermediate), VR module knowledge (intermediate), IRM module knowledge (intermediate), Technical writing (advanced).
Architecture & Performance Modeling Engineer EriduArchitecture & Performance Modeling EngineerSaratoga, CaliforniaYou will collaborate closely with system architects, chip designers, and cross-functional teams to evaluate design trade-offs, identify bottlenecks, and deliver actionable insights that shape the future of large-scale AI networking. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Research Engineer - Model Architectures ZyphraResearch Engineer - Model ArchitecturesSan Francisco, CaliforniaWe strongly value new and crazy ideas and are very willing to bet big on new ideas. Generally, a joy in inventing and seriously assessing ‘crazy’ ideas, and the ability to have a unique perspective on things.
Technical Program Manager, Architecture TenstorrentTechnical Program Manager, ArchitectureSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. The Technical Program Manager will drive the end-to-end execution of next-generation SoCs, from early architecture through RTL, verification, DFT, physical design, tape-out, and post-silicon validation.
NewPlatform Architecture Manager Intel CorpPlatform Architecture ManagerSanta Clara, CA$190,610–$361,480 / yearUnder a single-umbrella of leadership, PWCAs responsibilities are focused on integrating UX research, ecosystem engagement, competitive analysis, UX workflow development, and data collection into a single operating model that improves PXA's ability to make fast, evidence-based architecture and roadmap decisions. Strong working knowledge of user experience research methods, including framing research questions, selecting appropriate qualitative and quantitative approaches, evaluating research quality, and translating findings into actionable experience and platform requirements.
Sr. Staff Electrical Engineer, Vehicle Architecture ALSOSr. Staff Electrical Engineer, Vehicle ArchitecturePalo Alto, California$250,000–$280,000 / yearWe’re a passionate team of builders, dreamers, doers and innovators, focused on creating entirely new (not to mention, innovative and delightful) vertically integrated, small EVs designed to meet the global mobility challenges of today and tomorrow. Staff Electrical Engineer, Vehicle Architecture to drive the electrical architecture of our micro-mobility platforms, covering power distribution, energy storage, compute, sensors, lighting, safety systems, and connectivity.
NewStaff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU Samsung SemiconductorStaff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPUSan Jose, CA$163,000–$253,000 / yearThe role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed. The role offers broad ownership across architectural domains, with the opportunity to define new research directions, influence CPU architecture strategy, and drive ideas that can deliver meaningful performance gains in real hardware.
NewSenior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU Samsung SemiconductorSenior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPUSan Jose, CA$138,000–$206,000 / yearThe role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed. We develop and apply AI-driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation.