Principal Engineer, SerDes AMS Design and Architecture Ayar LabsPrincipal Engineer, SerDes AMS Design and ArchitectureSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Key Responsibilities: Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
Architecture & Performance Modeling Engineer EriduArchitecture & Performance Modeling EngineerSaratoga, CaliforniaYou will collaborate closely with system architects, chip designers, and cross-functional teams to evaluate design trade-offs, identify bottlenecks, and deliver actionable insights that shape the future of large-scale AI networking. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Research Scientist, (Privacy-Preserving Large-Scale Model Training & Architecture Optimization) TikTok IncResearch Scientist, (Privacy-Preserving Large-Scale Model Training & Architecture Optimization)San Jose, CAPrivacy-preserving and compliant training pipelines You will work on end-to-end training architecture design, from model-parallel execution and GPU efficiency to robust, fault-tolerant, privacy-aware training infrastructure. Design and optimize large-scale training architectures for diffusion-based and unified generative models (e.g., DiT, Rectified Flow, hybrid AR + diffusion systems).
Senior Director Power Architecture, Datacenter AI Qualcomm IncSenior Director Power Architecture, Datacenter AISanta Clara, CA$249,900–$375,800 / yearWork closely with supporting teams in design, architecture, emulation, firmware, design verification and software to ensure readiness for first silicon arrival, evaluation of AI and system performance upon silicon arrival, and evaluation of critical AI workloads. Drive technical innovation to enhance capabilities in system power validation including tools and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
CPU Architecture Performance Engineer (RISC V) Qualcomm IncCPU Architecture Performance Engineer (RISC V)Santa Clara, CA$167,100–$250,700 / yearMinimum Qualifications: Bachelor''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Master''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
CPU Micro-Architecture and RTL Design Engineer (RISC-V) Qualcomm IncCPU Micro-Architecture and RTL Design Engineer (RISC-V)Santa Clara, CA$167,100–$250,700 / yearThorough knowledge of microprocessor architecture including expertise in one or more of the following areas: instruction fetch and decode, branch prediction, instruction scheduling and register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache and memory subsystems. Minimum Qualifications: Bachelor''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Principal / Director - Robotics System Architecture Lead Qualcomm IncPrincipal / Director - Robotics System Architecture LeadSanta Clara, CA$242,300–$363,500 / yearGuide signal processing and sensor pipeline design (ISP, filtering, denoising, feature extraction, sensor fusion inputs), partnering with silicon and algorithm teams to meet accuracy, latency, and reliability targets. The ideal candidate is a recognized technical leader with deep robotics systems experience, strong architectural judgment, and the ability to influence cross-functional teams and long-term platform roadmaps.
Senior Architecture Energy Modeling Engineer NVIDIA CorpSenior Architecture Energy Modeling EngineerSanta Clara, CAYou will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next generation GPUs, CPUs and Tegra SOCs. Our team is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient; and is responsible for building energy models that integrate into architectural simulators, RTL simulation, emulation and silicon platforms.
Architecture Energy Modeling Engineer - New College Grad 2026 NVIDIA CorpArchitecture Energy Modeling Engineer - New College Grad 2026Santa Clara, CAYou will collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance Engineers, Software Engineers, and Physical Design teams to study and implement energy modeling techniques for NVIDIA's next generation GPUs, CPUs and Tegra SOCs. Our team is responsible for researching, developing, and deploying methodologies to help NVIDIA's products become more energy efficient; and is responsible for building energy models that integrate into architectural simulators, RTL simulation, emulation and silicon platforms.
Fellow, AI Software Architecture Advanced Micro Devices, IncFellow, AI Software ArchitectureSan Jose, CaliforniaAMD AI Group is seeking a highly influential technical leader for the role of AMD Fellow, OneROCm — driving a unified ROCm software stack across AMD’s broad product portfolio, including Instinct, Radeon, Ryzen, Embedded, Game Consoles, and Autonomous Driving platforms. As a s uccessful candidate , y ou are recognized for technical excellence, cross-functional leadership, and the ability to drive company-wide innovation through collaboration across silicon, system software, AI/ML frameworks, libraries, and application enablement teams.
Hardware System Architecture Fellow - AI & Data Center Networking Advanced Micro Devices, IncHardware System Architecture Fellow - AI & Data Center NetworkingSanta Clara, CaliforniaThe Fellow operates with enterprise‑scale technical authority, shaping multi‑generation system architectures and influencing execution across ASIC, packaging, board, optics, power, thermal, mechanical, firmware, and manufacturing domains, without direct people management responsibility. This role provides system‑level technical leadership, spanning architecture definition, cross‑domain trade‑offs, and resolution of the most complex hardware challenges across AI‑NICs, DPUs, switches, and rack‑scale networking solutions.
Engineering Manager - Architecture EfficientAI CorpEngineering Manager - ArchitectureSan Jose, CA$200,000–$240,000 / yearPlanning and tracking the work of the architecture team, including: Working closely with technical leads to prioritize work and set roadmaps based on business requirements from the Product, Sales and Marketing teams. This role owns the team''s operational cadence, including sprint planning, backlog management, project tracking, and cross-functional coordination to ensure projects are delivered on time.
System Architecture Fellow - AI & Data Center Networking Advanced Micro Devices IncSystem Architecture Fellow - AI & Data Center NetworkingSanta Clara, CATHE PERSON: The Fellow operates with enterprise‑scale technical authority, shaping multi‑generation system architectures and influencing execution across ASIC, package, board, optics, power, thermal, mechanical, firmware, and manufacturing domains without direct people management responsibility. This role focuses on system‑level technical leadership, spanning architecture definition, cross‑domain trade‑offs, and resolution of the most complex hardware challenges across AI‑NICs, DPUs, switches, and rack‑scale networking solutions.
Staff Technical Program Manager - Compliance Architecture Zscaler IncStaff Technical Program Manager - Compliance ArchitectureSan Jose, CARemote$119,000–$170,000 / yearDefine and maintain enterprise privacy baseline requirements, embedding them into the SDLC by translating regulatory and assurance expectations (e.g., NIST 800-53, FedRAMP/DoD IL5 privacy-relevant controls, and ISO 27701/ISO 42001) into measurable technical criteria and acceptance tests. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations and could be higher or lower based on a multitude of factors, including job-related skills, experience, and relevant education or training.
Sr. Staff Engineer, Electrical Link Architecture Ayar LabsSr. Staff Engineer, Electrical Link ArchitectureSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Joining our Link Design and Architecture team, you will own the electrical-side modeling that drives our silicon photonics I/O platform — the analog front end, the DSP that closes the link, and the models that make circuits and photonics co-simulate end-to-end.
NewSenior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU Samsung SemiconductorSenior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPUSan Jose, CaliforniaFull timeThe role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed. We develop and apply AI-driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation.
NewSenior Director, Architecture Research Lab Samsung SemiconductorSenior Director, Architecture Research LabSan Jose, CaliforniaFull timeThe role is responsible for end‑to‑end co‑design of AI workloads, system‑level modeling, hardware platforms, and high‑performance processors that leverage Samsung’s advanced memory technologies to eliminate capacity, bandwidth, and large‑scale communication bottlenecks. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
NewStaff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU Samsung SemiconductorStaff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPUSan Jose, CaliforniaFull timeThe role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed. The role offers broad ownership across architectural domains, with the opportunity to define new research directions, influence CPU architecture strategy, and drive ideas that can deliver meaningful performance gains in real hardware.
Dmts Of OCS System And Test Architecture LightWorks Optical SystemsDmts Of OCS System And Test ArchitectureSunnyvale, CATypically 12+ years of relevant experience in optical networking, photonic systems, complex electro-optical products, system architecture, or test engineering, including 5+ years leading multidisciplinary engineering teams and managers. Broad knowledge of optical communication systems, datacenter interconnect architectures, optical path and link budgets, loss, crosstalk, polarization and wavelength effects, and high-bandwidth, low-latency, energy-efficient system design.
DMTS of OCS System and Test Architecture Coherent CorpDMTS of OCS System and Test ArchitectureSunnyvale, CATypically 12+ years of relevant experience in optical networking, photonic systems, complex electro-optical products, system architecture, or test engineering, including 5+ years leading multidisciplinary engineering teams and managers. Lead architectural trade-offs across switching performance, port count and scalability, insertion loss, crosstalk, switching time, reliability, latency, power, thermal performance, cost, serviceability, manufacturability, security, and schedule.