Design axi/CHI interface, command scheduling, bank/rank/channel arbitration, QoS, refresh, power-state machines, and read/write turnaround under mixed AI, and real-time traffic. Deep understanding of DRAM internals: banks, ranks, channels, row/column timing (tRCD, tRP, tRAS, tRFC, tCCD, tWTR, tRTW), refresh, and page policy.