AIML enhanced Design/Verification Methodology Engineer Hewlett Packard Enterprise CoAIML enhanced Design/Verification Methodology EngineerSunnyvale, CA$81,400–$164,400 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. You will architect, build, and maintain UVM-based testbench environments, drive coverage-driven verification closure, and collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout.
Sr. Staff Engineer, ASIC Design Ayar Labs IncSr. Staff Engineer, ASIC DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff.
SoC Digital Design Engineer, Multimedia Lab TikTok IncSoC Digital Design Engineer, Multimedia LabSan Jose, CACross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Sr. Staff Engineer, Analog/Mixed-Signal Design Ayar Labs IncSr. Staff Engineer, Analog/Mixed-Signal DesignSan Jose, CA$180,000–$223,000 / yearBacked by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. As an Analog and Mixed Signal Design Engineer, you will design various blocks such as oscillators, high speed transmitters/receivers, biasing circuits, linear regulators, ADCs/DACs, and others.
Senior SoC Digital Design Engineer, Multimedia Lab TikTok IncSenior SoC Digital Design Engineer, Multimedia LabSan Jose, CACross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services.
Design Verification Engineer - Memory Subsystem Qualcomm IncDesign Verification Engineer - Memory SubsystemSanta Clara, CA$153,200–$229,800 / yearThe successful candidate will be responsible for developing and executing comprehensive verification strategies for complex digital designs, including memory controllers, DDR/LPDDR/HBM and custom memory interfaces, PHY-related logic, and other high-performance memory subsystem components. This role involves the complete verification lifecycle-from understanding design specifications and developing verification plans to creating UVM-based testbenches, developing assertions, executing simulations, debugging failures, and driving functional and code coverage closure.
Digital IC Design Engineer NeuralinkDigital IC Design EngineerSouth San Francisco, CA$116,000–$233,800 / yearJob Description & Responsibilities: Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.
Senior FPGA Design Engineer Anello PhotonicsSenior FPGA Design EngineerSanta Clara, CAThe ideal candidate has a strong background and can lead FPGA and hardware designs from concept through production, working closely with electrical, firmware, software, manufacturing, and test teams to deliver reliable, manufacturable products. This role requires strong expertise in FPGA architecture, RTL design, hardware validation, and board-level product development, including hands-on experience with PCBA design and system integration.
Standard Cell Design Lead Substrate IncStandard Cell Design LeadSan Francisco, CA$150,000–$275,000 / yearThis role requires deep expertise in digital cell design, layout, and timing characterization combined with strong understanding of library requirements for digital design flows. At the intersection of advanced manufacturing and cutting-edge physics, we are developing technologies that will reshape the semiconductor industry and strengthen Americas technological leadership.
Staff SoC Design Engineer Waymo LLCStaff SoC Design EngineerMountain View, CA$251,000–$310,000 / yearYou will: Define the architecture and microarchitecture for Waymo''s next-generation autonomous vehicle SoCs, translating system-level requirements into detailed hardware specifications and RTL implementation, using your knowledge of how hardware, firmware, drivers, and compilers interact. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World''s Most Experienced Driver-to improve access to mobility while saving thousands of lives now lost to traffic crashes.
Senior ASIC Design Verification Engineer, Google Cloud Google LLCSenior ASIC Design Verification Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Senior Manager, SoC Design Verification and Methodology Google LLCSenior Manager, SoC Design Verification and MethodologySunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. As a Senior Manager, System on a Chip (SoC) Design Verification and Methodology for Google"s TPU designs, you will lead a team and own the functional verification for key components by guiding the development of advanced methodologies and infrastructure at the subchip, subsystem, and full-chip levels.
Senior Design Verification CAD Engineer, Silicon, Google Cloud Google LLCSenior Design Verification CAD Engineer, Silicon, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Machine Learning Digital Design Engineer Meta Platforms IncMachine Learning Digital Design EngineerSunnyvale, CAContribute to ASIC digital µArchitecture and design Assist performance/power analysis of the design and help meet power and performance targets Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration Collaborate with adjacent teams such as Verification, Physical Design, and Design-for-Test Develop micro-architecture, RTL coding, and design verification for complex IPs Drive IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leadsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume Experience in digital design µArchitecture, RTL coding, and micro-architecture development Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams Experience in ML accelerator subsystems and top level design Experience in SoC integration and ASIC architecture Knowledge of microcontrollers, DSP, CDC and power sequence Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements) Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews) Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologiesMeta builds technologies that help people connect, find communities, and grow businesses. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.
ASIC Design Verification Engineer, Google Cloud Google LLCASIC Design Verification Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
TPU PCIe RTL Design Engineer Google LLCTPU PCIe RTL Design EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Join the team designing and developing the core components of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
Senior Digital Design Engineer Ethan Alexander GroupSenior Digital Design EngineerSanta Clara, CaliforniaAs a Senior Logic Design Engineer, you will be responsible for: Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD). Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
NewASIC Design Verification Manager, TPU Compute Google LLCASIC Design Verification Manager, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Lead the functional verification team for significant portions of TPU Compute team, setting and communicating individual and team priorities that support organizational goals, providing regular feedback and coaching, and developing advanced functional verification infrastructure such as subchip, subsystem, and fullchip level environments.
RTL Design Engineer, Machine Learning Google LLCRTL Design Engineer, Machine LearningSunnyvale, CAFrom software to hardware, our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research and much more. Youll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Hardware Engineer, Accelerator Design Meta Platforms IncHardware Engineer, Accelerator DesignMenlo Park, CAIn this role, you will work across digital design, power delivery, signal integrity, and board-level electrical engineering to bring accelerator systems from concept to production, directly enabling the AI workloads that power Meta's products and services. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.